From 47fd797f1ecd303da3263b180904a7a0b0e18581 Mon Sep 17 00:00:00 2001
From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Wed, 9 Jan 2019 20:10:29 +0000
Subject: arch-arm: Inital vector rename mode depending on A32/A64
Change-Id: I6b99833641b0ab6534471d5ff3ca5d3791285481
Reviewed-on: https://gem5-review.googlesource.com/c/15599
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
---
src/arch/arm/ArmISA.py | 4 ----
src/arch/arm/isa.cc | 6 +++++-
2 files changed, 5 insertions(+), 5 deletions(-)
(limited to 'src/arch/arm')
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 52c42cb95..b4e8536a0 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -87,10 +87,6 @@ class ArmISA(SimObject):
id_aa64afr1_el1 = Param.UInt64(0x0000000000000000,
"AArch64 Auxiliary Feature Register 1")
- # Initial vector register rename mode
- vecRegRenameMode = Param.VecRegRenameMode('Full',
- "Initial rename mode for vecregs")
-
# 1 CTX CMPs | 2 WRPs | 2 BRPs | !PMU | !Trace | Debug v8-A
id_aa64dfr0_el1 = Param.UInt64(0x0000000000101006,
"AArch64 Debug Feature Register 0")
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 6cbf8db90..97de97e6e 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -62,7 +62,7 @@ ISA::ISA(Params *p)
: SimObject(p),
system(NULL),
_decoderFlavour(p->decoderFlavour),
- _vecRegRenameMode(p->vecRegRenameMode),
+ _vecRegRenameMode(Enums::Full),
pmu(p->pmu),
impdefAsNop(p->impdef_nop)
{
@@ -103,6 +103,10 @@ ISA::ISA(Params *p)
haveGICv3CPUInterface = true;
}
+ // Initial rename mode depends on highestEL
+ const_cast<Enums::VecRegRenameMode&>(_vecRegRenameMode) =
+ highestELIs64 ? Enums::Full : Enums::Elem;
+
initializeMiscRegMetadata();
preUnflattenMiscReg();
--
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