From 4d5d47c173d3e649c7e620481d18ea93a3e09e79 Mon Sep 17 00:00:00 2001
From: Dylan Johnson <Dylan.Johnson@ARM.com>
Date: Tue, 2 Aug 2016 10:38:03 +0100
Subject: arm: Add TLBI instruction for stage 2 IPA's

This patch adds support for stage 2 TLBI instructions
such as TLBI IPAS2E1_Xt.

Change-Id: I0cd5e8055b0c1003e03439aa5183252f50ea0a88
---
 src/arch/arm/isa.cc | 23 +++++++++++++++++++++--
 src/arch/arm/tlb.cc |  7 +++++++
 src/arch/arm/tlb.hh | 13 +++++++++++++
 3 files changed, 41 insertions(+), 2 deletions(-)

(limited to 'src/arch/arm')

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 016e1eca0..fabbe0756 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1393,8 +1393,27 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
           case MISCREG_TLBI_IPAS2E1IS_Xt:
           case MISCREG_TLBI_IPAS2E1_Xt:
             assert64(tc);
-            // @todo: implement these as part of Virtualization
-            warn("Not doing anything for write of miscreg ITLB_IPAS2\n");
+            target_el = 1; // EL 0 and 1 are handled together
+            scr = readMiscReg(MISCREG_SCR, tc);
+            secure_lookup = haveSecurity && !scr.ns;
+            sys = tc->getSystemPtr();
+            for (x = 0; x < sys->numContexts(); x++) {
+                oc = sys->getThreadContext(x);
+                assert(oc->getITBPtr() && oc->getDTBPtr());
+                Addr ipa = ((Addr) bits(newVal, 35, 0)) << 12;
+                oc->getITBPtr()->flushIpaVmid(ipa,
+                    secure_lookup, false, target_el);
+                oc->getDTBPtr()->flushIpaVmid(ipa,
+                    secure_lookup, false, target_el);
+
+                CheckerCPU *checker = oc->getCheckerCpuPtr();
+                if (checker) {
+                    checker->getITBPtr()->flushIpaVmid(ipa,
+                        secure_lookup, false, target_el);
+                    checker->getDTBPtr()->flushIpaVmid(ipa,
+                        secure_lookup, false, target_el);
+                }
+            }
             return;
           case MISCREG_ACTLR:
             warn("Not doing anything for write of miscreg ACTLR\n");
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 9a44b1b58..a19a609b7 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -337,6 +337,13 @@ TLB::_flushMva(Addr mva, uint64_t asn, bool secure_lookup, bool hyp,
     }
 }
 
+void
+TLB::flushIpaVmid(Addr ipa, bool secure_lookup, bool hyp, uint8_t target_el)
+{
+    assert(!isStage2);
+    stage2Tlb->_flushMva(ipa, 0xbeef, secure_lookup, hyp, true, target_el);
+}
+
 bool
 TLB::checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el)
 {
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index ef05bb421..f4530a219 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -275,6 +275,19 @@ class TLB : public BaseTLB
      */
     void flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el);
 
+    /**
+     * Invalidate all entries in the stage 2 TLB that match the given ipa
+     * and the current VMID
+     * @param ipa the address to invalidate
+     * @param secure_lookup if the operation affects the secure world
+     * @param hyp if the operation affects hyp mode
+     */
+    void flushIpaVmid(Addr ipa, bool secure_lookup, bool hyp, uint8_t target_el);
+
+    Fault trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain);
+    Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec,
+            bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level);
+
     void printTlb() const;
 
     void demapPage(Addr vaddr, uint64_t asn) override
-- 
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