From 5187a24d496cd16bfe440f52ff0c45ab0e185306 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Wed, 4 Apr 2018 16:27:04 +0100 Subject: sim,cpu,mem,arch: Introduced MasterInfo data structure With this patch a gem5 System will store more info about its Masters. While it was previously keeping track of the Master name and Master ID only, it is now adding a per-Master pointer to the SimObject related to the Master. This will make it possible for a client to query a System for a Master using either the master's name or the master's pointer. Change-Id: I8b97d328a65cd06f329e2cdd3679451c17d2b8f6 Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/9781 Reviewed-by: Jason Lowe-Power Maintainer: Nikos Nikoleris --- src/arch/arm/stage2_mmu.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/arch/arm') diff --git a/src/arch/arm/stage2_mmu.cc b/src/arch/arm/stage2_mmu.cc index 5c28d073e..ba820e339 100644 --- a/src/arch/arm/stage2_mmu.cc +++ b/src/arch/arm/stage2_mmu.cc @@ -51,7 +51,7 @@ using namespace ArmISA; Stage2MMU::Stage2MMU(const Params *p) : SimObject(p), _stage1Tlb(p->tlb), _stage2Tlb(p->stage2_tlb), port(_stage1Tlb->getTableWalker(), p->sys), - masterId(p->sys->getMasterId(_stage1Tlb->getTableWalker()->name())) + masterId(p->sys->getMasterId(_stage1Tlb->getTableWalker())) { // we use the stage-one table walker as the parent of the port, // and to get our master id, this is done to keep things -- cgit v1.2.3