From 5299c75e62832aab2e200b22c73865ed9c51b335 Mon Sep 17 00:00:00 2001
From: Chander Sudanthi <chander.sudanthi@arm.com>
Date: Fri, 13 May 2011 17:27:00 -0500
Subject: ARM: Better RealView/Versatile EB platform support.

Add registers and components to better support the VersatileEB board.
Made the MIDR and SYS_ID register parameters to ArmSystem and RealviewCtrl
respectively.
---
 src/arch/arm/ArmSystem.py |  6 ++++++
 src/arch/arm/isa.cc       | 22 ++++++++--------------
 src/arch/arm/miscregs.hh  |  6 +++---
 src/arch/arm/system.cc    |  7 +++++++
 src/arch/arm/tlb.hh       |  5 +++++
 5 files changed, 29 insertions(+), 17 deletions(-)

(limited to 'src/arch/arm')

diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index e23ffd5a0..16cb2e549 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -46,6 +46,12 @@ class ArmMachineType(Enum):
 class ArmSystem(System):
     type = 'ArmSystem'
     load_addr_mask = 0xffffffff
+    # 0x35 Implementor is '5' from "M5"
+    # 0x0 Variant
+    # 0xf Architecture from CPUID scheme
+    # 0xf00 Primary part number
+    # 0x0 Revision
+    midr_regval = Param.UInt32(0x350ff000, "MIDR value")
     boot_loader = Param.String("", "File that contains the boot loader code if any")
     boot_loader_mem = Param.PhysicalMemory(NULL,
                           "Memory object that boot loader is to be loaded into")
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index a92813697..0db941462 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -52,7 +52,7 @@ void
 ISA::clear()
 {
     SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
-
+    uint32_t midr = miscRegs[MISCREG_MIDR];
     memset(miscRegs, 0, sizeof(miscRegs));
     CPSR cpsr = 0;
     cpsr.mode = MODE_USER;
@@ -71,21 +71,12 @@ ISA::clear()
     miscRegs[MISCREG_SCTLR] = sctlr;
     miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
 
+    // Preserve MIDR accross reset
+    miscRegs[MISCREG_MIDR] = midr;
+
     /* Start with an event in the mailbox */
     miscRegs[MISCREG_SEV_MAILBOX] = 1;
 
-    /*
-     * Implemented = '5' from "M5",
-     * Variant = 0,
-     */
-    miscRegs[MISCREG_MIDR] =
-        (0x35 << 24) | // Implementor is '5' from "M5"
-        (0 << 20)    | // Variant
-        (0xf << 16)  | // Architecture from CPUID scheme
-        (0xf00 << 4) | // Primary part number
-        (0 << 0)     | // Revision
-        0;
-
     // Separate Instruction and Data TLBs.
     miscRegs[MISCREG_TLBTR] = 1;
 
@@ -209,6 +200,9 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
         warn("Returning thumbEE disabled for now since we don't support CP14"
              "config registers and jumping to ThumbEE vectors\n");
         return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM
+      case MISCREG_ID_PFR1:
+        warn("reading unimplmented register ID_PFR1");
+        return 0;
       case MISCREG_ID_MMFR0:
         return 0x03; //VMSAz7
       case MISCREG_CTR:
@@ -219,7 +213,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
       case MISCREG_PMCR:
       case MISCREG_PMCCNTR:
       case MISCREG_PMSELR:
-        warn("Not doing anyhting for read to miscreg %s\n",
+        warn("Not doing anything for read to miscreg %s\n",
                 miscRegName[misc_reg]);
         break;
       case MISCREG_FPSCR_QC:
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index f87cc3ad5..c506455f8 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -174,9 +174,9 @@ namespace ArmISA
         MISCREG_CPSR_MODE,
         MISCREG_LOCKFLAG,
         MISCREG_LOCKADDR,
+        MISCREG_ID_PFR1,
         MISCREG_CP15_UNIMP_START,
         MISCREG_TCMTR = MISCREG_CP15_UNIMP_START,
-        MISCREG_ID_PFR1,
         MISCREG_ID_DFR0,
         MISCREG_ID_AFR0,
         MISCREG_ID_MMFR1,
@@ -236,10 +236,10 @@ namespace ArmISA
         "pmceid1", "pmc_other", "pmxevcntr",
         "pmuserenr", "pmintenset", "pmintenclr",
         "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
-        "cpsr_mode", "lockflag", "lockaddr",
+        "cpsr_mode", "lockflag", "lockaddr", "id_pfr1",
          // Unimplemented below
         "tcmtr",
-        "id_pfr1", "id_dfr0", "id_afr0",
+        "id_dfr0", "id_afr0",
         "id_mmfr1", "id_mmfr2",
         "aidr", "adfsr", "aifsr",
         "dcimvac", "dcisw", "mccsw",
diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index 8431bfff2..4d4dff4d9 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -104,6 +104,13 @@ ArmSystem::initState()
         // Set the initial PC to be at start of the kernel code
         threadContexts[0]->pcState(kernelEntry & loadAddrMask);
     }
+    for (int i = 0; i < threadContexts.size(); i++) {
+        if (params()->midr_regval) {
+            threadContexts[i]->setMiscReg(ArmISA::MISCREG_MIDR,
+                    params()->midr_regval);
+        }
+    }
+
 }
 
 ArmSystem::~ArmSystem()
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 269128c2a..bf6ae22f8 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -236,6 +236,11 @@ protected:
         miscRegValid = true;
     }
 public:
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
     inline void invalidateMiscReg() { miscRegValid = false; }
 };
 
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