From 59e3585a84ef172eba57c9936680c0248f9a97db Mon Sep 17 00:00:00 2001 From: "yuetsu.kodama" Date: Sat, 20 Oct 2018 11:58:54 +0900 Subject: arch-arm: We add PRFM PST instruction for arm Note current PRFM supports only PLD, but PST (prefetch for store) is also important for latency hiding. We also bug fix in disassembler to display prfop correctly. Change-Id: I9144e7233900aa2d555e1c1a6a2c2e41d837aa13 Signed-off-by: Yuetsu Kodama Reviewed-on: https://gem5-review.googlesource.com/c/13675 Reviewed-by: Jason Lowe-Power Reviewed-by: Nikos Nikoleris Reviewed-by: Giacomo Travaglini Maintainer: Andreas Sandberg --- src/arch/arm/insts/mem64.cc | 6 +++++- src/arch/arm/insts/static_inst.cc | 10 ++++++++++ src/arch/arm/isa/insts/ldr64.isa | 15 ++++++++++----- 3 files changed, 25 insertions(+), 6 deletions(-) (limited to 'src/arch/arm') diff --git a/src/arch/arm/insts/mem64.cc b/src/arch/arm/insts/mem64.cc index fa8fdf0af..660e56e80 100644 --- a/src/arch/arm/insts/mem64.cc +++ b/src/arch/arm/insts/mem64.cc @@ -64,7 +64,11 @@ void Memory64::startDisassembly(std::ostream &os) const { printMnemonic(os, "", false); - printIntReg(os, dest); + if (isDataPrefetch()||isInstPrefetch()){ + printPFflags(os, dest); + }else{ + printIntReg(os, dest); + } ccprintf(os, ", ["); printIntReg(os, base); } diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc index bd6f11521..f245cd4f0 100644 --- a/src/arch/arm/insts/static_inst.cc +++ b/src/arch/arm/insts/static_inst.cc @@ -324,6 +324,16 @@ ArmStaticInst::printIntReg(std::ostream &os, RegIndex reg_idx) const } } +void ArmStaticInst::printPFflags(std::ostream &os, int flag) const +{ + const char *flagtoprfop[]= { "PLD", "PLI", "PST", "Reserved"}; + const char *flagtotarget[] = { "L1", "L2", "L3", "Reserved"}; + const char *flagtopolicy[] = { "KEEP", "STRM"}; + + ccprintf(os, "%s%s%s", flagtoprfop[(flag>>3)&3], + flagtotarget[(flag>>1)&3], flagtopolicy[flag&1]); +} + void ArmStaticInst::printFloatReg(std::ostream &os, RegIndex reg_idx) const { diff --git a/src/arch/arm/isa/insts/ldr64.isa b/src/arch/arm/isa/insts/ldr64.isa index 7c177263d..54e50d73e 100644 --- a/src/arch/arm/isa/insts/ldr64.isa +++ b/src/arch/arm/isa/insts/ldr64.isa @@ -74,6 +74,10 @@ let {{ elif self.flavor == "iprefetch": self.memFlags.append("Request::PREFETCH") self.instFlags = ['IsInstPrefetch'] + elif self.flavor == "mprefetch": + self.memFlags.append("((((dest>>3)&3)==2)? \ + (Request::PF_EXCLUSIVE):(Request::PREFETCH))") + self.instFlags = ['IsDataPrefetch'] if self.micro: self.instFlags.append("IsMicroop") @@ -176,7 +180,7 @@ let {{ self.buildEACode() # Code that actually handles the access - if self.flavor in ("dprefetch", "iprefetch"): + if self.flavor in ("dprefetch", "iprefetch", "mprefetch"): accCode = 'uint64_t temp M5_VAR_USED = Mem%s;' elif self.flavor == "fp": if self.size in (1, 2, 4): @@ -365,10 +369,11 @@ let {{ buildLoads64("ldr", "LDRSFP64", 4, False, flavor="fp") buildLoads64("ldr", "LDRDFP64", 8, False, flavor="fp") - LoadImm64("prfm", "PRFM64_IMM", 8, flavor="dprefetch").emit() - LoadReg64("prfm", "PRFM64_REG", 8, flavor="dprefetch").emit() - LoadLit64("prfm", "PRFM64_LIT", 8, literal=True, flavor="dprefetch").emit() - LoadImm64("prfum", "PRFUM64_IMM", 8, flavor="dprefetch").emit() + LoadImm64("prfm", "PRFM64_IMM", 8, flavor="mprefetch").emit() + LoadReg64("prfm", "PRFM64_REG", 8, flavor="mprefetch").emit() + LoadLit64("prfm", "PRFM64_LIT", 8, literal=True, + flavor="mprefetch").emit() + LoadImm64("prfum", "PRFUM64_IMM", 8, flavor="mprefetch").emit() LoadImm64("ldurb", "LDURB64_IMM", 1, False).emit() LoadImm64("ldursb", "LDURSBW64_IMM", 1, True).emit() -- cgit v1.2.3