From 5f59e195d61c9144c817aab4a9179036adad6c9c Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Mon, 15 Nov 2010 14:04:05 -0600
Subject: ARM: Add comment about the organization of the IT state register

---
 src/arch/arm/miscregs.hh | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'src/arch/arm')

diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index aa3f47419..2bb1cdb15 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -262,6 +262,12 @@ namespace ArmISA
     EndBitUnion(CPSR)
 
     BitUnion8(ITSTATE)
+        /* Note that the split (cond, mask) below is not as in ARM ARM.
+         * But it is more convenient for simulation. The condition
+         * is always the concatenation of the top 3 bits and the next bit,
+         * which applies when one of the bottom 4 bits is set.
+         * Refer to predecoder.cc for the use case.
+         */
         Bitfield<7, 4> cond;
         Bitfield<3, 0> mask;
         // Bitfields for moving to/from CPSR
-- 
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