From 608641e23c7f2288810c3f23a1a63790b664f2ab Mon Sep 17 00:00:00 2001
From: Nilay Vaish <nilay@cs.wisc.edu>
Date: Sun, 26 Jul 2015 10:21:20 -0500
Subject: cpu: implements vector registers

This adds a vector register type.  The type is defined as a std::array of a
fixed number of uint64_ts.  The isa_parser.py has been modified to parse vector
register operands and generate the required code.  Different cpus have vector
register files now.
---
 src/arch/arm/insts/static_inst.cc |  2 ++
 src/arch/arm/isa.hh               |  7 +++++++
 src/arch/arm/registers.hh         | 10 +++++++++-
 src/arch/arm/utility.cc           |  3 +++
 4 files changed, 21 insertions(+), 1 deletion(-)

(limited to 'src/arch/arm')

diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc
index 9f878ac4d..417496579 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -337,6 +337,8 @@ ArmStaticInst::printReg(std::ostream &os, int reg) const
       case CCRegClass:
         ccprintf(os, "cc_%s", ArmISA::ccRegName[rel_reg]);
         break;
+      case VectorRegClass:
+        panic("ARM ISA does not have any vector registers yet!");
     }
 }
 
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index a07017c17..1e7edd637 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -287,6 +287,13 @@ namespace ArmISA
             return reg;
         }
 
+        int
+        flattenVectorIndex(int reg) const
+        {
+            assert(reg >= 0);
+            return reg;
+        }
+
         int
         flattenMiscIndex(int reg) const
         {
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index 23fc20450..e57802e53 100644
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -72,6 +72,12 @@ typedef uint64_t MiscReg;
 // condition code register; must be at least 32 bits for FpCondCodes
 typedef uint64_t CCReg;
 
+// vector register file entry type
+typedef uint64_t VectorRegElement;
+const int NumVectorRegElements = 0;
+const int VectorRegBytes = NumVectorRegElements * sizeof(VectorRegElement);
+typedef std::array<VectorRegElement, NumVectorRegElements> VectorReg;
+
 // Constants Related to the number of registers
 const int NumIntArchRegs = NUM_ARCH_INTREGS;
 // The number of single precision floating point registers
@@ -82,6 +88,7 @@ const int NumFloatSpecialRegs = 32;
 const int NumIntRegs = NUM_INTREGS;
 const int NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs;
 const int NumCCRegs = NUM_CCREGS;
+const int NumVectorRegs = 0;
 const int NumMiscRegs = NUM_MISCREGS;
 
 #define ISA_HAS_CC_REGS
@@ -112,7 +119,8 @@ const int SyscallSuccessReg = ReturnValueReg;
 // These help enumerate all the registers for dependence tracking.
 const int FP_Reg_Base = NumIntRegs * (MODE_MAXMODE + 1);
 const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs;
-const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs;
+const int Vector_Reg_Base = CC_Reg_Base + NumCCRegs;
+const int Misc_Reg_Base = Vector_Reg_Base + NumVectorRegs;
 const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
 
 typedef union {
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 34fcfd482..e1f9dfe04 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -156,6 +156,9 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
     for (int i = 0; i < NumCCRegs; i++)
         dest->setCCReg(i, src->readCCReg(i));
 
+    // Copy vector registers when vector registers put to use.
+    assert(NumVectorRegs == 0);
+
     for (int i = 0; i < NumMiscRegs; i++)
         dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
 
-- 
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