From 72538294fb1eb2e4dcd5d818c78bcdf78b0de491 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Mon, 19 Mar 2012 06:36:09 -0400 Subject: gcc: Clean-up of non-C++0x compliant code, first steps This patch cleans up a number of minor issues aiming to get closer to compliance with the C++0x standard as interpreted by gcc and clang (compile with std=c++0x and -pedantic-errors). In particular, the patch cleans up enums where the last item was succeded by a comma, namespaces closed by a curcly brace followed by a semi-colon, and the use of the GNU-extension typeof (replaced by templated functions). It does not address variable-length arrays, zero-size arrays, anonymous structs, range expressions in switch statements, and the use of long long. The generated CPU code also has a large number of issues that remain to be fixed, mainly related to overflows in implicit constant conversion (due to shifts). --- src/arch/arm/intregs.hh | 2 +- src/arch/arm/isa/templates/neon.isa | 18 +++++++++++------- src/arch/arm/linux/atag.hh | 2 +- src/arch/arm/miscregs.cc | 2 +- src/arch/arm/miscregs.hh | 2 +- src/arch/arm/nativetrace.cc | 2 +- src/arch/arm/pagetable.hh | 2 +- src/arch/arm/predecoder.hh | 2 +- src/arch/arm/table_walker.hh | 2 +- src/arch/arm/utility.hh | 2 +- src/arch/arm/vtophys.hh | 2 +- 11 files changed, 21 insertions(+), 17 deletions(-) (limited to 'src/arch/arm') diff --git a/src/arch/arm/intregs.hh b/src/arch/arm/intregs.hh index c26e36211..3fe00b765 100644 --- a/src/arch/arm/intregs.hh +++ b/src/arch/arm/intregs.hh @@ -239,7 +239,7 @@ enum IntRegIndex INTREG_R6_FIQ = INTREG_R6, INTREG_R7_FIQ = INTREG_R7, INTREG_PC_FIQ = INTREG_PC, - INTREG_R15_FIQ = INTREG_R15, + INTREG_R15_FIQ = INTREG_R15 }; typedef IntRegIndex IntRegMap[NUM_ARCH_INTREGS]; diff --git a/src/arch/arm/isa/templates/neon.isa b/src/arch/arm/isa/templates/neon.isa index fe3a026b8..573d245b8 100644 --- a/src/arch/arm/isa/templates/neon.isa +++ b/src/arch/arm/isa/templates/neon.isa @@ -234,12 +234,16 @@ def template NeonEqualRegExecute {{ }}; output header {{ - uint16_t nextBiggerType(uint8_t); - uint32_t nextBiggerType(uint16_t); - uint64_t nextBiggerType(uint32_t); - int16_t nextBiggerType(int8_t); - int32_t nextBiggerType(int16_t); - int64_t nextBiggerType(int32_t); + template + struct bigger_type_t; + + template<> struct bigger_type_t { typedef uint16_t type; }; + template<> struct bigger_type_t { typedef uint32_t type; }; + template<> struct bigger_type_t { typedef uint64_t type; }; + + template<> struct bigger_type_t { typedef int16_t type; }; + template<> struct bigger_type_t { typedef int32_t type; }; + template<> struct bigger_type_t { typedef int64_t type; }; }}; def template NeonUnequalRegExecute {{ @@ -247,7 +251,7 @@ def template NeonUnequalRegExecute {{ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { - typedef typeof(nextBiggerType((Element)0)) BigElement; + typedef typename bigger_type_t::type BigElement; Fault fault = NoFault; %(op_decl)s; %(op_rd)s; diff --git a/src/arch/arm/linux/atag.hh b/src/arch/arm/linux/atag.hh index 71271dac2..88bd2da4c 100644 --- a/src/arch/arm/linux/atag.hh +++ b/src/arch/arm/linux/atag.hh @@ -51,7 +51,7 @@ enum { RevTag = 0x54410007, SerialTag = 0x54410006, CmdTag = 0x54410009, - NoneTag = 0x00000000, + NoneTag = 0x00000000 }; class AtagHeader diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index 286ecc1de..73f92cabb 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -499,4 +499,4 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) return NUM_MISCREGS; } -}; +} diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index a20fd0c61..8fba5101b 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -529,6 +529,6 @@ namespace ArmISA Bitfield<31> l2rstDISABLE_monitor; EndBitUnion(L2CTLR) -}; +} #endif // __ARCH_ARM_MISCREGS_HH__ diff --git a/src/arch/arm/nativetrace.cc b/src/arch/arm/nativetrace.cc index 875ceae31..21dff8b7c 100644 --- a/src/arch/arm/nativetrace.cc +++ b/src/arch/arm/nativetrace.cc @@ -226,4 +226,4 @@ Trace::ArmNativeTrace * ArmNativeTraceParams::create() { return new Trace::ArmNativeTrace(this); -}; +} diff --git a/src/arch/arm/pagetable.hh b/src/arch/arm/pagetable.hh index 2c86d3d84..898ab3191 100644 --- a/src/arch/arm/pagetable.hh +++ b/src/arch/arm/pagetable.hh @@ -208,6 +208,6 @@ struct TlbEntry -}; +} #endif // __ARCH_ARM_PAGETABLE_H__ diff --git a/src/arch/arm/predecoder.hh b/src/arch/arm/predecoder.hh index 188f675bb..87ba1777c 100644 --- a/src/arch/arm/predecoder.hh +++ b/src/arch/arm/predecoder.hh @@ -149,6 +149,6 @@ namespace ArmISA return thisEmi; } }; -}; +} #endif // __ARCH_ARM_PREDECODER_HH__ diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh index 22d2da5b3..b5099bb27 100644 --- a/src/arch/arm/table_walker.hh +++ b/src/arch/arm/table_walker.hh @@ -325,7 +325,7 @@ class TableWalker : public MemObject /** Queue of requests that have passed are waiting because the walker is * currently busy. */ - std::list pendingQueue;; + std::list pendingQueue; /** Port to issue translation requests from */ diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh index ffd41791c..b3b400e3c 100644 --- a/src/arch/arm/utility.hh +++ b/src/arch/arm/utility.hh @@ -182,6 +182,6 @@ getExecutingAsid(ThreadContext *tc) return tc->readMiscReg(MISCREG_CONTEXTIDR); } -}; +} #endif diff --git a/src/arch/arm/vtophys.hh b/src/arch/arm/vtophys.hh index 12a6c6ec6..56181d318 100644 --- a/src/arch/arm/vtophys.hh +++ b/src/arch/arm/vtophys.hh @@ -45,7 +45,7 @@ namespace ArmISA { Addr vtophys(Addr vaddr); Addr vtophys(ThreadContext *tc, Addr vaddr); bool virtvalid(ThreadContext *tc, Addr vaddr); -}; +} #endif // __ARCH_ARM_VTOPHYS_H__ -- cgit v1.2.3