From 8ddec45de48ddca443064212600c2583df2fe882 Mon Sep 17 00:00:00 2001 From: Giacomo Gabrielli Date: Wed, 8 Nov 2017 16:06:12 +0000 Subject: arch-arm: Add initial support for SVE contiguous loads/stores Thanks to Pau Cabre and Adria Armejach Sanosa for their contribution of bugfixes. Change-Id: If8983cf85d95cddb187c90967a94ddfe2414bc46 Signed-off-by: Giacomo Gabrielli Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13519 Tested-by: kokoro Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini --- src/arch/arm/SConscript | 1 + src/arch/arm/insts/sve_mem.cc | 116 ++++++++ src/arch/arm/insts/sve_mem.hh | 153 ++++++++++ src/arch/arm/isa/formats/sve_2nd_level.isa | 316 ++++++++++++++++++++ src/arch/arm/isa/includes.isa | 1 + src/arch/arm/isa/insts/insts.isa | 1 + src/arch/arm/isa/insts/sve_mem.isa | 453 +++++++++++++++++++++++++++++ src/arch/arm/isa/templates/sve.isa | 2 +- src/arch/arm/isa/templates/sve_mem.isa | 386 ++++++++++++++++++++++++ src/arch/arm/isa/templates/templates.isa | 1 + 10 files changed, 1429 insertions(+), 1 deletion(-) create mode 100644 src/arch/arm/insts/sve_mem.cc create mode 100644 src/arch/arm/insts/sve_mem.hh create mode 100644 src/arch/arm/isa/insts/sve_mem.isa create mode 100644 src/arch/arm/isa/templates/sve_mem.isa (limited to 'src/arch/arm') diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript index 58a13cd72..caea1c470 100644 --- a/src/arch/arm/SConscript +++ b/src/arch/arm/SConscript @@ -61,6 +61,7 @@ if env['TARGET_ISA'] == 'arm': Source('insts/pseudo.cc') Source('insts/static_inst.cc') Source('insts/sve.cc') + Source('insts/sve_mem.cc') Source('insts/vfp.cc') Source('insts/fplib.cc') Source('insts/crypto.cc') diff --git a/src/arch/arm/insts/sve_mem.cc b/src/arch/arm/insts/sve_mem.cc new file mode 100644 index 000000000..0f24d899b --- /dev/null +++ b/src/arch/arm/insts/sve_mem.cc @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2017 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Giacomo Gabrielli + */ + +#include "arch/arm/insts/sve_mem.hh" + +namespace ArmISA +{ + +std::string +SveMemVecFillSpill::generateDisassembly(Addr pc, + const SymbolTable *symtab) const +{ + std::stringstream ss; + printMnemonic(ss, "", false); + printVecReg(ss, dest, true); + ccprintf(ss, ", ["); + printIntReg(ss, base); + if (imm != 0) { + ccprintf(ss, ", #%d, mul vl", imm); + } + ccprintf(ss, "]"); + return ss.str(); +} + +std::string +SveMemPredFillSpill::generateDisassembly(Addr pc, + const SymbolTable *symtab) const +{ + std::stringstream ss; + printMnemonic(ss, "", false); + printVecPredReg(ss, dest); + ccprintf(ss, ", ["); + printIntReg(ss, base); + if (imm != 0) { + ccprintf(ss, ", #%d, mul vl", imm); + } + ccprintf(ss, "]"); + return ss.str(); +} + +std::string +SveContigMemSS::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + // TODO: add suffix to transfer register and scaling factor (LSL #) + std::stringstream ss; + printMnemonic(ss, "", false); + ccprintf(ss, "{"); + printVecReg(ss, dest, true); + ccprintf(ss, "}, "); + printVecPredReg(ss, gp); + ccprintf(ss, "/z, "); + ccprintf(ss, ", ["); + printIntReg(ss, base); + ccprintf(ss, ", "); + printIntReg(ss, offset); + ccprintf(ss, "]"); + return ss.str(); +} + +std::string +SveContigMemSI::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + // TODO: add suffix to transfer register + std::stringstream ss; + printMnemonic(ss, "", false); + ccprintf(ss, "{"); + printVecReg(ss, dest, true); + ccprintf(ss, "}, "); + printVecPredReg(ss, gp); + ccprintf(ss, "/z, "); + ccprintf(ss, ", ["); + printIntReg(ss, base); + if (imm != 0) { + ccprintf(ss, ", #%d, mul vl", imm); + } + ccprintf(ss, "]"); + return ss.str(); +} + +} // namespace ArmISA diff --git a/src/arch/arm/insts/sve_mem.hh b/src/arch/arm/insts/sve_mem.hh new file mode 100644 index 000000000..de6b69cd5 --- /dev/null +++ b/src/arch/arm/insts/sve_mem.hh @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2017 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Giacomo Gabrielli + */ + +#ifndef __ARCH_ARM_SVE_MEM_HH__ +#define __ARCH_ARM_SVE_MEM_HH__ + +#include "arch/arm/insts/static_inst.hh" +#include "arch/arm/tlb.hh" + +namespace ArmISA +{ + +class SveMemVecFillSpill : public ArmStaticInst +{ + protected: + IntRegIndex dest; + IntRegIndex base; + uint64_t imm; + + /// True if the base register is SP (used for SP alignment checking). + bool baseIsSP; + + unsigned memAccessFlags; + + SveMemVecFillSpill(const char *mnem, ExtMachInst _machInst, + OpClass __opClass, IntRegIndex _dest, + IntRegIndex _base, uint64_t _imm) + : ArmStaticInst(mnem, _machInst, __opClass), + dest(_dest), base(_base), imm(_imm), + memAccessFlags(ArmISA::TLB::AllowUnaligned | ArmISA::TLB::MustBeOne) + { + baseIsSP = isSP(_base); + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; +}; + +class SveMemPredFillSpill : public ArmStaticInst +{ + protected: + IntRegIndex dest; + IntRegIndex base; + uint64_t imm; + + /// True if the base register is SP (used for SP alignment checking). + bool baseIsSP; + + unsigned memAccessFlags; + + SveMemPredFillSpill(const char *mnem, ExtMachInst _machInst, + OpClass __opClass, IntRegIndex _dest, + IntRegIndex _base, uint64_t _imm) + : ArmStaticInst(mnem, _machInst, __opClass), + dest(_dest), base(_base), imm(_imm), + memAccessFlags(ArmISA::TLB::AllowUnaligned | ArmISA::TLB::MustBeOne) + { + baseIsSP = isSP(_base); + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; +}; + +class SveContigMemSS : public ArmStaticInst +{ + protected: + IntRegIndex dest; + IntRegIndex gp; + IntRegIndex base; + IntRegIndex offset; + + /// True if the base register is SP (used for SP alignment checking). + bool baseIsSP; + + unsigned memAccessFlags; + + SveContigMemSS(const char *mnem, ExtMachInst _machInst, OpClass __opClass, + IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base, + IntRegIndex _offset) + : ArmStaticInst(mnem, _machInst, __opClass), + dest(_dest), gp(_gp), base(_base), offset(_offset), + memAccessFlags(ArmISA::TLB::AllowUnaligned | ArmISA::TLB::MustBeOne) + { + baseIsSP = isSP(_base); + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; +}; + +class SveContigMemSI : public ArmStaticInst +{ + protected: + IntRegIndex dest; + IntRegIndex gp; + IntRegIndex base; + uint64_t imm; + + /// True if the base register is SP (used for SP alignment checking). + bool baseIsSP; + + unsigned memAccessFlags; + + SveContigMemSI(const char *mnem, ExtMachInst _machInst, OpClass __opClass, + IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base, + uint64_t _imm) + : ArmStaticInst(mnem, _machInst, __opClass), + dest(_dest), gp(_gp), base(_base), imm(_imm), + memAccessFlags(ArmISA::TLB::AllowUnaligned | ArmISA::TLB::MustBeOne) + { + baseIsSP = isSP(_base); + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; +}; + +} // namespace ArmISA + +#endif // __ARCH_ARM_SVE_MEM_HH__ diff --git a/src/arch/arm/isa/formats/sve_2nd_level.isa b/src/arch/arm/isa/formats/sve_2nd_level.isa index ff7e50ee5..e81ab3ed7 100644 --- a/src/arch/arm/isa/formats/sve_2nd_level.isa +++ b/src/arch/arm/isa/formats/sve_2nd_level.isa @@ -2896,12 +2896,152 @@ namespace Aarch64 StaticInstPtr decodeSveMemGather32(ExtMachInst machInst) { + // TODO: for now only LDR and LD1R are implemented + if (bits(machInst, 22) && bits(machInst, 15)) { + IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0); + IntRegIndex rn = makeSP( + (IntRegIndex) (uint8_t) bits(machInst, 9, 5)); + uint64_t imm = bits(machInst, 21, 16); + IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10); + uint8_t dtype = (bits(machInst, 24, 23) << 2) | + bits(machInst, 14, 13); + return decodeSveContigLoadSIInsts( + dtype, machInst, zt, pg, rn, imm, false, true); + } else if (bits(machInst, 24, 22) == 0x6 && + bits(machInst, 15, 13) == 0x0 && + bits(machInst, 4) == 0x0) { + IntRegIndex pt = (IntRegIndex) (uint8_t) bits(machInst, 3, 0); + IntRegIndex rn = makeSP( + (IntRegIndex) (uint8_t) bits(machInst, 9, 5)); + uint64_t imm = sext<9>((bits(machInst, 21, 16) << 3) | + bits(machInst, 12, 10)); + return new SveLdrPred(machInst, pt, rn, imm); + } else if (bits(machInst, 24, 22) == 0x6 && + bits(machInst, 15, 13) == 0x2) { + IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0); + IntRegIndex rn = makeSP( + (IntRegIndex) (uint8_t) bits(machInst, 9, 5)); + uint64_t imm = sext<9>((bits(machInst, 21, 16) << 3) | + bits(machInst, 12, 10)); + return new SveLdrVec(machInst, zt, rn, imm); + } return new Unknown64(machInst); } // decodeSveMemGather32 + StaticInstPtr + decodeSveLoadBcastQuadSS(ExtMachInst machInst) + { + return new Unknown64(machInst); + } // decodeSveLoadBcastQuadSS + + StaticInstPtr + decodeSveLoadBcastQuadSI(ExtMachInst machInst) + { + return new Unknown64(machInst); + } // decodeSveLoadBcastQuadSI + + StaticInstPtr + decodeSveContigLoadSS(ExtMachInst machInst) + { + IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0); + IntRegIndex rn = makeSP((IntRegIndex) (uint8_t) bits(machInst, 9, 5)); + IntRegIndex rm = makeSP( + (IntRegIndex) (uint8_t) bits(machInst, 20, 16)); + IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10); + + if (rm == 0x1f) { + return new Unknown64(machInst); + } + + return decodeSveContigLoadSSInsts( + bits(machInst, 24, 21), machInst, zt, pg, rn, rm, false); + } // decodeSveContigLoadSS + + StaticInstPtr + decodeSveContigFFLoadSS(ExtMachInst machInst) + { + return new Unknown64(machInst); + } // decodeSveContigFFLoadSS + + StaticInstPtr + decodeSveContigLoadSI(ExtMachInst machInst) + { + IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0); + IntRegIndex rn = makeSP((IntRegIndex) (uint8_t) bits(machInst, 9, 5)); + uint64_t imm = sext<4>(bits(machInst, 19, 16)); + IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10); + + return decodeSveContigLoadSIInsts( + bits(machInst, 24, 21), machInst, zt, pg, rn, imm, false); + } // decodeSveContigLoadSI + + StaticInstPtr + decodeSveContigNFLoadSI(ExtMachInst machInst) + { + return new Unknown64(machInst); + } // decodeSveContigNFLoadSI + + StaticInstPtr + decodeSveContigNTLoadSS(ExtMachInst machInst) + { + return new Unknown64(machInst); + } // decodeSveContigNTLoadSS + + StaticInstPtr + decodeSveLoadStructsSS(ExtMachInst machInst) + { + return new Unknown64(machInst); + } // decodeSveLoadStructsSS + + StaticInstPtr + decodeSveContigNTLoadSI(ExtMachInst machInst) + { + return new Unknown64(machInst); + } // decodeSveContigNTLoadSI + + StaticInstPtr + decodeSveLoadStructsSI(ExtMachInst machInst) + { + return new Unknown64(machInst); + } // decodeSveLoadStructsSI + StaticInstPtr decodeSveMemContigLoad(ExtMachInst machInst) { + switch (bits(machInst, 15, 13)) { + case 0x0: + return decodeSveLoadBcastQuadSS(machInst); + case 0x1: + if (bits(machInst, 20) == 0x0) { + return decodeSveLoadBcastQuadSI(machInst); + } + break; + case 0x2: + return decodeSveContigLoadSS(machInst); + case 0x3: + return decodeSveContigFFLoadSS(machInst); + case 0x5: + if (bits(machInst, 20) == 0x0) { + return decodeSveContigLoadSI(machInst); + } else { + return decodeSveContigNFLoadSI(machInst); + } + case 0x6: + if (bits(machInst, 22, 21) == 0x0) { + return decodeSveContigNTLoadSS(machInst); + } else { + return decodeSveLoadStructsSS(machInst); + } + case 0x7: + if (bits(machInst, 20) == 0) { + if (bits(machInst, 22, 21) == 0x0) { + return decodeSveContigNTLoadSI(machInst); + } else { + return decodeSveLoadStructsSI(machInst); + } + } + break; + } return new Unknown64(machInst); } // decodeSveMemContigLoad @@ -2911,9 +3051,185 @@ namespace Aarch64 return new Unknown64(machInst); } // decodeSveMemGather64 + StaticInstPtr + decodeSveContigStoreSS(ExtMachInst machInst) + { + IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0); + IntRegIndex rn = makeSP((IntRegIndex) (uint8_t) bits(machInst, 9, 5)); + IntRegIndex rm = makeSP( + (IntRegIndex) (uint8_t) bits(machInst, 20, 16)); + IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10); + + if (rm == 0x1f) { + return new Unknown64(machInst); + } + + return decodeSveContigStoreSSInsts( + bits(machInst, 24, 21), machInst, zt, pg, rn, rm); + } // decodeSveContigStoreSS + + StaticInstPtr + decodeSveContigStoreSI(ExtMachInst machInst) + { + IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0); + IntRegIndex rn = makeSP((IntRegIndex) (uint8_t) bits(machInst, 9, 5)); + int8_t imm = sext<4>(bits(machInst, 19, 16)); + IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10); + + return decodeSveContigStoreSIInsts( + bits(machInst, 24, 21), machInst, zt, pg, rn, imm); + } // decodeSveContigStoreSI + + StaticInstPtr + decodeSveContigNTStoreSS(ExtMachInst machInst) + { + return new Unknown64(machInst); + } // decodeSveContigNTStoreSS + + StaticInstPtr + decodeSveScatterStore64SV32U(ExtMachInst machInst) + { + return new Unknown64(machInst); + } // decodeSveScatterStore64SV32U + + StaticInstPtr + decodeSveScatterStore64SV64U(ExtMachInst machInst) + { + return new Unknown64(machInst); + } // decodeSveScatterStore64SV64U + + StaticInstPtr + decodeSveContigNTStoreSI(ExtMachInst machInst) + { + return new Unknown64(machInst); + } // decodeSveContigNTStoreSI + + StaticInstPtr + decodeSveScatterStore64VI(ExtMachInst machInst) + { + return new Unknown64(machInst); + } // decodeSveScatterStore64VI + + StaticInstPtr + decodeSveScatterStore32SV32S(ExtMachInst machInst) + { + return new Unknown64(machInst); + } // decodeSveScatterStore32SV32S + + StaticInstPtr + decodeSveStoreStructsSS(ExtMachInst machInst) + { + return new Unknown64(machInst); + } // decodeSveStoreStructsSS + + StaticInstPtr + decodeSveStoreStructsSI(ExtMachInst machInst) + { + return new Unknown64(machInst); + } // decodeSveStoreStructsSI + + StaticInstPtr + decodeSveScatterStore32SV32U(ExtMachInst machInst) + { + return new Unknown64(machInst); + } // decodeSveScatterStore32SV32U + + StaticInstPtr + decodeSveScatterStore32VI(ExtMachInst machInst) + { + return new Unknown64(machInst); + } // decodeSveScatterStore32VI + + StaticInstPtr + decodeSveScatterStore64SV32S(ExtMachInst machInst) + { + return new Unknown64(machInst); + } // decodeSveScatterStore64SV32S + + StaticInstPtr + decodeSveScatterStore64SV64S(ExtMachInst machInst) + { + return new Unknown64(machInst); + } // decodeSveScatterStore64SV64S + StaticInstPtr decodeSveMemStore(ExtMachInst machInst) { + switch (bits(machInst, 15, 13)) { + case 0x0: + if (bits(machInst, 24, 22) == 0x6 && bits(machInst, 4) == 0x0) { + IntRegIndex pt = (IntRegIndex) (uint8_t) bits(machInst, 3, 0); + IntRegIndex rn = makeSP( + (IntRegIndex) (uint8_t) bits(machInst, 9, 5)); + int16_t imm = sext<9>((bits(machInst, 21, 16) << 3) | + bits(machInst, 12, 10)); + return new SveStrPred(machInst, pt, rn, imm); + } + break; + case 0x2: + if (bits(machInst, 24, 22) == 0x6) { + IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0); + IntRegIndex rn = makeSP( + (IntRegIndex) (uint8_t) bits(machInst, 9, 5)); + int16_t imm = sext<9>((bits(machInst, 21, 16) << 3) | + bits(machInst, 12, 10)); + return new SveStrVec(machInst, zt, rn, imm); + } else { + return decodeSveContigStoreSS(machInst); + } + break; + case 0x3: + if (bits(machInst, 22, 21) == 0x0) { + return decodeSveContigNTStoreSS(machInst); + } else { + return decodeSveStoreStructsSS(machInst); + } + case 0x4: + case 0x6: + switch (bits(machInst, 22, 21)) { + case 0x0: + return decodeSveScatterStore64SV32U(machInst); + case 0x1: + if (bits(machInst, 24, 23) != 0x0) { + return decodeSveScatterStore64SV32S(machInst); + } + break; + case 0x2: + if (bits(machInst, 24, 23) != 0x3) { + return decodeSveScatterStore32SV32U(machInst); + } + break; + case 0x3: + return decodeSveScatterStore32SV32S(machInst); + } + break; + case 0x5: + switch (bits(machInst, 22, 21)) { + case 0x0: + return decodeSveScatterStore64SV64U(machInst); + case 0x1: + if (bits(machInst, 24, 23) != 0x0) { + return decodeSveScatterStore64SV64S(machInst); + } + break; + case 0x2: + return decodeSveScatterStore64VI(machInst); + case 0x3: + if (bits(machInst, 24, 23) != 0x3) { + return decodeSveScatterStore64VI(machInst); + } + break; + } + break; + case 0x7: + if (bits(machInst, 20) == 0x0) { + return decodeSveContigStoreSI(machInst); + } else if (bits(machInst, 22, 21) == 0x0) { + return decodeSveContigNTStoreSI(machInst); + } else { + return decodeSveStoreStructsSI(machInst); + } + } return new Unknown64(machInst); } // decodeSveMemStore diff --git a/src/arch/arm/isa/includes.isa b/src/arch/arm/isa/includes.isa index b89a67432..9aef8c651 100644 --- a/src/arch/arm/isa/includes.isa +++ b/src/arch/arm/isa/includes.isa @@ -65,6 +65,7 @@ output header {{ #include "arch/arm/insts/pseudo.hh" #include "arch/arm/insts/static_inst.hh" #include "arch/arm/insts/sve.hh" +#include "arch/arm/insts/sve_mem.hh" #include "arch/arm/insts/vfp.hh" #include "arch/arm/isa_traits.hh" #include "mem/packet.hh" diff --git a/src/arch/arm/isa/insts/insts.isa b/src/arch/arm/isa/insts/insts.isa index 623657efc..a1b35efc4 100644 --- a/src/arch/arm/isa/insts/insts.isa +++ b/src/arch/arm/isa/insts/insts.isa @@ -99,6 +99,7 @@ split decoder; //SVE ##include "sve.isa" +##include "sve_mem.isa" //m5 Pseudo-ops ##include "m5ops.isa" diff --git a/src/arch/arm/isa/insts/sve_mem.isa b/src/arch/arm/isa/insts/sve_mem.isa new file mode 100644 index 000000000..f4ca4c3c9 --- /dev/null +++ b/src/arch/arm/isa/insts/sve_mem.isa @@ -0,0 +1,453 @@ +// Copyright (c) 2017 ARM Limited +// All rights reserved +// +// The license below extends only to copyright in the software and shall +// not be construed as granting a license to any other intellectual +// property including but not limited to intellectual property relating +// to a hardware implementation of the functionality of the software +// licensed hereunder. You may use the software subject to the license +// terms below provided that you ensure that this notice is replicated +// unmodified and in its entirety in all distributions of the software, +// modified or unmodified, in source code or in binary form. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer; +// redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution; +// neither the name of the copyright holders nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Authors: Giacomo Gabrielli + +// @file Definition of SVE memory access instructions. + +output header {{ + + // Decodes SVE contiguous load instructions, scalar plus scalar form. + template