From 997cbe1c09f6ffff6bee11bb374e3a32601d0f06 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Mon, 26 Sep 2011 23:48:54 -0700
Subject: ISA parser: Use '_' instead of '.' to delimit type modifiers on
 operands.

By using an underscore, the "." is still available and can unambiguously be
used to refer to members of a structure if an operand is a structure, class,
etc. This change mostly just replaces the appropriate "."s with "_"s, but
there were also a few places where the ISA descriptions where handling the
extensions themselves and had their own regular expressions to update. The
regular expressions in the isa parser were updated as well. It also now
looks for one of the defined type extensions specifically after connecting "_"
where before it would look for any sequence of characters after a "."
following an operand name and try to use it as the extension. This helps to
disambiguate cases where a "_" may legitimately be part of an operand name but
not separate the name from the type suffix.

Because leaving the "_" and suffix on the variable name still leaves a valid
C++ identifier and all extensions need to be consistent in a given context, I
considered leaving them on as a breadcrumb that would show what the intended
type was for that operand. Unfortunately the operands can be referred to in
code templates, the Mem operand in particular, and since the exact type of Mem
can be different for different uses of the same template, that broke things.
---
 src/arch/arm/isa/insts/branch.isa   |   4 +-
 src/arch/arm/isa/insts/data.isa     | 156 ++++++++++----------
 src/arch/arm/isa/insts/div.isa      |  16 +-
 src/arch/arm/isa/insts/fp.isa       | 284 ++++++++++++++++++------------------
 src/arch/arm/isa/insts/ldr.isa      |  16 +-
 src/arch/arm/isa/insts/macromem.isa |  66 ++++-----
 src/arch/arm/isa/insts/mem.isa      |   8 +-
 src/arch/arm/isa/insts/misc.isa     |   8 +-
 src/arch/arm/isa/insts/mult.isa     | 160 ++++++++++----------
 src/arch/arm/isa/insts/neon.isa     | 118 +++++++--------
 src/arch/arm/isa/insts/str.isa      |  16 +-
 src/arch/arm/isa/insts/swap.isa     |   6 +-
 12 files changed, 429 insertions(+), 429 deletions(-)

(limited to 'src/arch/arm')

diff --git a/src/arch/arm/isa/insts/branch.isa b/src/arch/arm/isa/insts/branch.isa
index 767c07835..e360f4581 100644
--- a/src/arch/arm/isa/insts/branch.isa
+++ b/src/arch/arm/isa/insts/branch.isa
@@ -172,7 +172,7 @@ let {{
                                       ArmISA::TLB::MustBeOne;
             EA = Op1 + Op2 * 2
             '''
-            accCode = 'NPC = PC + 2 * (Mem.uh);\n'
+            accCode = 'NPC = PC + 2 * (Mem_uh);\n'
             mnem = "tbh"
         else:
             eaCode = '''
@@ -181,7 +181,7 @@ let {{
                                       ArmISA::TLB::MustBeOne;
             EA = Op1 + Op2
             '''
-            accCode = 'NPC = PC + 2 * (Mem.ub)'
+            accCode = 'NPC = PC + 2 * (Mem_ub)'
             mnem = "tbb"
         iop = InstObjParams(mnem, mnem.capitalize(), "BranchRegReg",
                             {'ea_code': eaCode,
diff --git a/src/arch/arm/isa/insts/data.isa b/src/arch/arm/isa/insts/data.isa
index 09f9621f1..89c0e48c7 100644
--- a/src/arch/arm/isa/insts/data.isa
+++ b/src/arch/arm/isa/insts/data.isa
@@ -302,7 +302,7 @@ let {{
 
     buildRegDataInst("qadd", '''
             int32_t midRes;
-            resTemp = saturateOp<32>(midRes, Op1.sw, Op2.sw);
+            resTemp = saturateOp<32>(midRes, Op1_sw, Op2_sw);
                                      Dest = midRes;
         ''', flagType="saturate", buildNonCc=False)
     buildRegDataInst("qadd16", '''
@@ -310,8 +310,8 @@ let {{
             for (unsigned i = 0; i < 2; i++) {
                 int high = (i + 1) * 16 - 1;
                 int low = i * 16;
-                int64_t arg1 = sext<16>(bits(Op1.sw, high, low));
-                int64_t arg2 = sext<16>(bits(Op2.sw, high, low));
+                int64_t arg1 = sext<16>(bits(Op1_sw, high, low));
+                int64_t arg2 = sext<16>(bits(Op2_sw, high, low));
                 saturateOp<16>(midRes, arg1, arg2);
                 replaceBits(resTemp, high, low, midRes);
             }
@@ -322,8 +322,8 @@ let {{
             for (unsigned i = 0; i < 4; i++) {
                 int high = (i + 1) * 8 - 1;
                 int low = i * 8;
-                int64_t arg1 = sext<8>(bits(Op1.sw, high, low));
-                int64_t arg2 = sext<8>(bits(Op2.sw, high, low));
+                int64_t arg1 = sext<8>(bits(Op1_sw, high, low));
+                int64_t arg2 = sext<8>(bits(Op2_sw, high, low));
                 saturateOp<8>(midRes, arg1, arg2);
                 replaceBits(resTemp, high, low, midRes);
             }
@@ -331,13 +331,13 @@ let {{
         ''', flagType="none", buildCc=False)
     buildRegDataInst("qdadd", '''
             int32_t midRes;
-            resTemp = saturateOp<32>(midRes, Op2.sw, Op2.sw) |
-                      saturateOp<32>(midRes, Op1.sw, midRes);
+            resTemp = saturateOp<32>(midRes, Op2_sw, Op2_sw) |
+                      saturateOp<32>(midRes, Op1_sw, midRes);
             Dest = midRes;
         ''', flagType="saturate", buildNonCc=False)
     buildRegDataInst("qsub", '''
             int32_t midRes;
-            resTemp = saturateOp<32>(midRes, Op1.sw, Op2.sw, true);
+            resTemp = saturateOp<32>(midRes, Op1_sw, Op2_sw, true);
             Dest = midRes;
         ''', flagType="saturate")
     buildRegDataInst("qsub16", '''
@@ -345,8 +345,8 @@ let {{
             for (unsigned i = 0; i < 2; i++) {
                  int high = (i + 1) * 16 - 1;
                  int low = i * 16;
-                 int64_t arg1 = sext<16>(bits(Op1.sw, high, low));
-                 int64_t arg2 = sext<16>(bits(Op2.sw, high, low));
+                 int64_t arg1 = sext<16>(bits(Op1_sw, high, low));
+                 int64_t arg2 = sext<16>(bits(Op2_sw, high, low));
                  saturateOp<16>(midRes, arg1, arg2, true);
                  replaceBits(resTemp, high, low, midRes);
             }
@@ -357,8 +357,8 @@ let {{
             for (unsigned i = 0; i < 4; i++) {
                  int high = (i + 1) * 8 - 1;
                  int low = i * 8;
-                 int64_t arg1 = sext<8>(bits(Op1.sw, high, low));
-                 int64_t arg2 = sext<8>(bits(Op2.sw, high, low));
+                 int64_t arg1 = sext<8>(bits(Op1_sw, high, low));
+                 int64_t arg2 = sext<8>(bits(Op2_sw, high, low));
                  saturateOp<8>(midRes, arg1, arg2, true);
                  replaceBits(resTemp, high, low, midRes);
             }
@@ -366,16 +366,16 @@ let {{
         ''', flagType="none", buildCc=False)
     buildRegDataInst("qdsub", '''
             int32_t midRes;
-            resTemp = saturateOp<32>(midRes, Op2.sw, Op2.sw) |
-                      saturateOp<32>(midRes, Op1.sw, midRes, true);
+            resTemp = saturateOp<32>(midRes, Op2_sw, Op2_sw) |
+                      saturateOp<32>(midRes, Op1_sw, midRes, true);
             Dest = midRes;
         ''', flagType="saturate", buildNonCc=False)
     buildRegDataInst("qasx", '''
             int32_t midRes;
-            int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0));
-            int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16));
-            int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0));
-            int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16));
+            int64_t arg1Low = sext<16>(bits(Op1_sw, 15, 0));
+            int64_t arg1High = sext<16>(bits(Op1_sw, 31, 16));
+            int64_t arg2Low = sext<16>(bits(Op2_sw, 15, 0));
+            int64_t arg2High = sext<16>(bits(Op2_sw, 31, 16));
             saturateOp<16>(midRes, arg1Low, arg2High, true);
             replaceBits(resTemp, 15, 0, midRes);
             saturateOp<16>(midRes, arg1High, arg2Low);
@@ -384,10 +384,10 @@ let {{
         ''', flagType="none", buildCc=False)
     buildRegDataInst("qsax", '''
             int32_t midRes;
-            int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0));
-            int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16));
-            int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0));
-            int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16));
+            int64_t arg1Low = sext<16>(bits(Op1_sw, 15, 0));
+            int64_t arg1High = sext<16>(bits(Op1_sw, 31, 16));
+            int64_t arg2Low = sext<16>(bits(Op2_sw, 15, 0));
+            int64_t arg2High = sext<16>(bits(Op2_sw, 31, 16));
             saturateOp<16>(midRes, arg1Low, arg2High);
             replaceBits(resTemp, 15, 0, midRes);
             saturateOp<16>(midRes, arg1High, arg2Low, true);
@@ -401,8 +401,8 @@ let {{
             for (unsigned i = 0; i < 4; i++) {
                 int high = (i + 1) * 8 - 1;
                 int low = i * 8;
-                int32_t midRes = sext<8>(bits(Op1.sw, high, low)) +
-                                 sext<8>(bits(Op2.sw, high, low));
+                int32_t midRes = sext<8>(bits(Op1_sw, high, low)) +
+                                 sext<8>(bits(Op2_sw, high, low));
                 replaceBits(resTemp, high, low, midRes);
                 if (midRes >= 0) {
                     geBits = geBits | (1 << i);
@@ -417,8 +417,8 @@ let {{
             for (unsigned i = 0; i < 2; i++) {
                 int high = (i + 1) * 16 - 1;
                 int low = i * 16;
-                int32_t midRes = sext<16>(bits(Op1.sw, high, low)) +
-                                 sext<16>(bits(Op2.sw, high, low));
+                int32_t midRes = sext<16>(bits(Op1_sw, high, low)) +
+                                 sext<16>(bits(Op2_sw, high, low));
                 replaceBits(resTemp, high, low, midRes);
                 if (midRes >= 0) {
                     geBits = geBits | (0x3 << (i * 2));
@@ -434,8 +434,8 @@ let {{
             for (unsigned i = 0; i < 4; i++) {
                 int high = (i + 1) * 8 - 1;
                 int low = i * 8;
-                int32_t midRes = sext<8>(bits(Op1.sw, high, low)) -
-                                 sext<8>(bits(Op2.sw, high, low));
+                int32_t midRes = sext<8>(bits(Op1_sw, high, low)) -
+                                 sext<8>(bits(Op2_sw, high, low));
                 replaceBits(resTemp, high, low, midRes);
                 if (midRes >= 0) {
                     geBits = geBits | (1 << i);
@@ -450,8 +450,8 @@ let {{
             for (unsigned i = 0; i < 2; i++) {
                 int high = (i + 1) * 16 - 1;
                 int low = i * 16;
-                int32_t midRes = sext<16>(bits(Op1.sw, high, low)) -
-                                 sext<16>(bits(Op2.sw, high, low));
+                int32_t midRes = sext<16>(bits(Op1_sw, high, low)) -
+                                 sext<16>(bits(Op2_sw, high, low));
                 replaceBits(resTemp, high, low, midRes);
                 if (midRes >= 0) {
                     geBits = geBits | (0x3 << (i * 2));
@@ -463,10 +463,10 @@ let {{
     buildRegDataInst("sasx", '''
             int32_t midRes, geBits = 0;
             resTemp = 0;
-            int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0));
-            int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16));
-            int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0));
-            int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16));
+            int64_t arg1Low = sext<16>(bits(Op1_sw, 15, 0));
+            int64_t arg1High = sext<16>(bits(Op1_sw, 31, 16));
+            int64_t arg2Low = sext<16>(bits(Op2_sw, 15, 0));
+            int64_t arg2High = sext<16>(bits(Op2_sw, 31, 16));
             midRes = arg1Low - arg2High;
             if (midRes >= 0) {
                 geBits = geBits | 0x3;
@@ -483,10 +483,10 @@ let {{
     buildRegDataInst("ssax", '''
             int32_t midRes, geBits = 0;
             resTemp = 0;
-            int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0));
-            int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16));
-            int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0));
-            int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16));
+            int64_t arg1Low = sext<16>(bits(Op1_sw, 15, 0));
+            int64_t arg1High = sext<16>(bits(Op1_sw, 31, 16));
+            int64_t arg2Low = sext<16>(bits(Op2_sw, 15, 0));
+            int64_t arg2High = sext<16>(bits(Op2_sw, 31, 16));
             midRes = arg1Low + arg2High;
             if (midRes >= 0) {
                 geBits = geBits | 0x3;
@@ -507,8 +507,8 @@ let {{
                 int high = (i + 1) * 8 - 1;
                 int low = i * 8;
                 int32_t midRes =
-                    (uint64_t)(sext<8>(bits(Op1.sw, high, low)) +
-                               sext<8>(bits(Op2.sw, high, low))) >> 1;
+                    (uint64_t)(sext<8>(bits(Op1_sw, high, low)) +
+                               sext<8>(bits(Op2_sw, high, low))) >> 1;
                 replaceBits(resTemp, high, low, midRes);
             }
             Dest = resTemp;
@@ -519,8 +519,8 @@ let {{
                 int high = (i + 1) * 16 - 1;
                 int low = i * 16;
                 int32_t midRes =
-                    (uint64_t)(sext<16>(bits(Op1.sw, high, low)) +
-                               sext<16>(bits(Op2.sw, high, low))) >> 1;
+                    (uint64_t)(sext<16>(bits(Op1_sw, high, low)) +
+                               sext<16>(bits(Op2_sw, high, low))) >> 1;
                 replaceBits(resTemp, high, low, midRes);
             }
             Dest = resTemp;
@@ -531,8 +531,8 @@ let {{
                 int high = (i + 1) * 8 - 1;
                 int low = i * 8;
                 int32_t midRes =
-                    (uint64_t)(sext<8>(bits(Op1.sw, high, low)) -
-                               sext<8>(bits(Op2.sw, high, low))) >> 1;
+                    (uint64_t)(sext<8>(bits(Op1_sw, high, low)) -
+                               sext<8>(bits(Op2_sw, high, low))) >> 1;
                 replaceBits(resTemp, high, low, midRes);
             }
             Dest = resTemp;
@@ -543,8 +543,8 @@ let {{
                 int high = (i + 1) * 16 - 1;
                 int low = i * 16;
                 int32_t midRes =
-                    (uint64_t)(sext<16>(bits(Op1.sw, high, low)) -
-                               sext<16>(bits(Op2.sw, high, low))) >> 1;
+                    (uint64_t)(sext<16>(bits(Op1_sw, high, low)) -
+                               sext<16>(bits(Op2_sw, high, low))) >> 1;
                 replaceBits(resTemp, high, low, midRes);
             }
             Dest = resTemp;
@@ -552,10 +552,10 @@ let {{
     buildRegDataInst("shasx", '''
             int32_t midRes;
             resTemp = 0;
-            int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0));
-            int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16));
-            int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0));
-            int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16));
+            int64_t arg1Low = sext<16>(bits(Op1_sw, 15, 0));
+            int64_t arg1High = sext<16>(bits(Op1_sw, 31, 16));
+            int64_t arg2Low = sext<16>(bits(Op2_sw, 15, 0));
+            int64_t arg2High = sext<16>(bits(Op2_sw, 31, 16));
             midRes = (uint64_t)(arg1Low - arg2High) >> 1;
             replaceBits(resTemp, 15, 0, midRes);
             midRes = (arg1High + arg2Low) >> 1;
@@ -565,10 +565,10 @@ let {{
     buildRegDataInst("shsax", '''
             int32_t midRes;
             resTemp = 0;
-            int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0));
-            int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16));
-            int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0));
-            int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16));
+            int64_t arg1Low = sext<16>(bits(Op1_sw, 15, 0));
+            int64_t arg1High = sext<16>(bits(Op1_sw, 31, 16));
+            int64_t arg2Low = sext<16>(bits(Op2_sw, 15, 0));
+            int64_t arg2High = sext<16>(bits(Op2_sw, 31, 16));
             midRes = (uint64_t)(arg1Low + arg2High) >> 1;
             replaceBits(resTemp, 15, 0, midRes);
             midRes = (uint64_t)(arg1High - arg2Low) >> 1;
@@ -626,10 +626,10 @@ let {{
         ''', flagType="none", buildCc=False)
     buildRegDataInst("uqasx", '''
             uint32_t midRes;
-            uint64_t arg1Low = bits(Op1.sw, 15, 0);
-            uint64_t arg1High = bits(Op1.sw, 31, 16);
-            uint64_t arg2Low = bits(Op2.sw, 15, 0);
-            uint64_t arg2High = bits(Op2.sw, 31, 16);
+            uint64_t arg1Low = bits(Op1_sw, 15, 0);
+            uint64_t arg1High = bits(Op1_sw, 31, 16);
+            uint64_t arg2Low = bits(Op2_sw, 15, 0);
+            uint64_t arg2High = bits(Op2_sw, 31, 16);
             uSaturateOp<16>(midRes, arg1Low, arg2High, true);
             replaceBits(resTemp, 15, 0, midRes);
             uSaturateOp<16>(midRes, arg1High, arg2Low);
@@ -638,10 +638,10 @@ let {{
         ''', flagType="none", buildCc=False)
     buildRegDataInst("uqsax", '''
             uint32_t midRes;
-            uint64_t arg1Low = bits(Op1.sw, 15, 0);
-            uint64_t arg1High = bits(Op1.sw, 31, 16);
-            uint64_t arg2Low = bits(Op2.sw, 15, 0);
-            uint64_t arg2High = bits(Op2.sw, 31, 16);
+            uint64_t arg1Low = bits(Op1_sw, 15, 0);
+            uint64_t arg1High = bits(Op1_sw, 31, 16);
+            uint64_t arg2Low = bits(Op2_sw, 15, 0);
+            uint64_t arg2High = bits(Op2_sw, 31, 16);
             uSaturateOp<16>(midRes, arg1Low, arg2High);
             replaceBits(resTemp, 15, 0, midRes);
             uSaturateOp<16>(midRes, arg1High, arg2Low, true);
@@ -716,10 +716,10 @@ let {{
     buildRegDataInst("uasx", '''
             int32_t midRes, geBits = 0;
             resTemp = 0;
-            int64_t arg1Low = bits(Op1.sw, 15, 0);
-            int64_t arg1High = bits(Op1.sw, 31, 16);
-            int64_t arg2Low = bits(Op2.sw, 15, 0);
-            int64_t arg2High = bits(Op2.sw, 31, 16);
+            int64_t arg1Low = bits(Op1_sw, 15, 0);
+            int64_t arg1High = bits(Op1_sw, 31, 16);
+            int64_t arg2Low = bits(Op2_sw, 15, 0);
+            int64_t arg2High = bits(Op2_sw, 31, 16);
             midRes = arg1Low - arg2High;
             if (midRes >= 0) {
                 geBits = geBits | 0x3;
@@ -736,10 +736,10 @@ let {{
     buildRegDataInst("usax", '''
             int32_t midRes, geBits = 0;
             resTemp = 0;
-            int64_t arg1Low = bits(Op1.sw, 15, 0);
-            int64_t arg1High = bits(Op1.sw, 31, 16);
-            int64_t arg2Low = bits(Op2.sw, 15, 0);
-            int64_t arg2High = bits(Op2.sw, 31, 16);
+            int64_t arg1Low = bits(Op1_sw, 15, 0);
+            int64_t arg1High = bits(Op1_sw, 31, 16);
+            int64_t arg2Low = bits(Op2_sw, 15, 0);
+            int64_t arg2High = bits(Op2_sw, 31, 16);
             midRes = arg1Low + arg2High;
             if (midRes >= 0x10000) {
                 geBits = geBits | 0x3;
@@ -801,10 +801,10 @@ let {{
     buildRegDataInst("uhasx", '''
             int32_t midRes;
             resTemp = 0;
-            int64_t arg1Low = bits(Op1.sw, 15, 0);
-            int64_t arg1High = bits(Op1.sw, 31, 16);
-            int64_t arg2Low = bits(Op2.sw, 15, 0);
-            int64_t arg2High = bits(Op2.sw, 31, 16);
+            int64_t arg1Low = bits(Op1_sw, 15, 0);
+            int64_t arg1High = bits(Op1_sw, 31, 16);
+            int64_t arg2Low = bits(Op2_sw, 15, 0);
+            int64_t arg2High = bits(Op2_sw, 31, 16);
             midRes = (arg1Low - arg2High) >> 1;
             replaceBits(resTemp, 15, 0, midRes);
             midRes = (arg1High + arg2Low) >> 1;
@@ -814,10 +814,10 @@ let {{
     buildRegDataInst("uhsax", '''
             int32_t midRes;
             resTemp = 0;
-            int64_t arg1Low = bits(Op1.sw, 15, 0);
-            int64_t arg1High = bits(Op1.sw, 31, 16);
-            int64_t arg2Low = bits(Op2.sw, 15, 0);
-            int64_t arg2High = bits(Op2.sw, 31, 16);
+            int64_t arg1Low = bits(Op1_sw, 15, 0);
+            int64_t arg1High = bits(Op1_sw, 31, 16);
+            int64_t arg2Low = bits(Op2_sw, 15, 0);
+            int64_t arg2High = bits(Op2_sw, 31, 16);
             midRes = (arg1Low + arg2High) >> 1;
             replaceBits(resTemp, 15, 0, midRes);
             midRes = (arg1High - arg2Low) >> 1;
diff --git a/src/arch/arm/isa/insts/div.isa b/src/arch/arm/isa/insts/div.isa
index d736f9230..8a94d1ebd 100644
--- a/src/arch/arm/isa/insts/div.isa
+++ b/src/arch/arm/isa/insts/div.isa
@@ -39,7 +39,7 @@
 
 let {{
     sdivCode = '''
-    if (Op2.sw == 0) {
+    if (Op2_sw == 0) {
         if (((SCTLR)Sctlr).dz) {
 #if FULL_SYSTEM
             return new UndefinedInstruction;
@@ -47,11 +47,11 @@ let {{
             return new UndefinedInstruction(false, mnemonic);
 #endif
         }
-        Dest.sw = 0;
-    } else if (Op1.sw == INT_MIN && Op2.sw == -1) {
-        Dest.sw = INT_MIN;
+        Dest_sw = 0;
+    } else if (Op1_sw == INT_MIN && Op2_sw == -1) {
+        Dest_sw = INT_MIN;
     } else {
-        Dest.sw = Op1.sw / Op2.sw;
+        Dest_sw = Op1_sw / Op2_sw;
     }
     '''
     sdivIop = InstObjParams("sdiv", "Sdiv", "RegRegRegOp",
@@ -63,7 +63,7 @@ let {{
     exec_output = PredOpExecute.subst(sdivIop)
 
     udivCode = '''
-    if (Op2.uw == 0) {
+    if (Op2_uw == 0) {
         if (((SCTLR)Sctlr).dz) {
 #if FULL_SYSTEM
             return new UndefinedInstruction;
@@ -71,9 +71,9 @@ let {{
             return new UndefinedInstruction(false, mnemonic);
 #endif
         }
-        Dest.uw = 0;
+        Dest_uw = 0;
     } else {
-        Dest.uw = Op1.uw / Op2.uw;
+        Dest_uw = Op1_uw / Op2_uw;
     }
     '''
     udivIop = InstObjParams("udiv", "Udiv", "RegRegRegOp",
diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa
index 73b3aa50e..f82858bbd 100644
--- a/src/arch/arm/isa/insts/fp.isa
+++ b/src/arch/arm/isa/insts/fp.isa
@@ -250,7 +250,7 @@ let {{
     exec_output += PredOpExecute.subst(vmrsApsrFpscrIop);
 
     vmovImmSCode = vfpEnabledCheckCode + '''
-        FpDest.uw = bits(imm, 31, 0);
+        FpDest_uw = bits(imm, 31, 0);
     '''
     vmovImmSIop = InstObjParams("vmov", "VmovImmS", "FpRegImmOp",
                                 { "code": vmovImmSCode,
@@ -261,8 +261,8 @@ let {{
     exec_output += PredOpExecute.subst(vmovImmSIop);
 
     vmovImmDCode = vfpEnabledCheckCode + '''
-        FpDestP0.uw = bits(imm, 31, 0);
-        FpDestP1.uw = bits(imm, 63, 32);
+        FpDestP0_uw = bits(imm, 31, 0);
+        FpDestP1_uw = bits(imm, 63, 32);
     '''
     vmovImmDIop = InstObjParams("vmov", "VmovImmD", "FpRegImmOp",
                                 { "code": vmovImmDCode,
@@ -273,10 +273,10 @@ let {{
     exec_output += PredOpExecute.subst(vmovImmDIop);
 
     vmovImmQCode = vfpEnabledCheckCode + '''
-        FpDestP0.uw = bits(imm, 31, 0);
-        FpDestP1.uw = bits(imm, 63, 32);
-        FpDestP2.uw = bits(imm, 31, 0);
-        FpDestP3.uw = bits(imm, 63, 32);
+        FpDestP0_uw = bits(imm, 31, 0);
+        FpDestP1_uw = bits(imm, 63, 32);
+        FpDestP2_uw = bits(imm, 31, 0);
+        FpDestP3_uw = bits(imm, 63, 32);
     '''
     vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "FpRegImmOp",
                                 { "code": vmovImmQCode,
@@ -287,7 +287,7 @@ let {{
     exec_output += PredOpExecute.subst(vmovImmQIop);
 
     vmovRegSCode = vfpEnabledCheckCode + '''
-        FpDest.uw = FpOp1.uw;
+        FpDest_uw = FpOp1_uw;
     '''
     vmovRegSIop = InstObjParams("vmov", "VmovRegS", "FpRegRegOp",
                                 { "code": vmovRegSCode,
@@ -298,8 +298,8 @@ let {{
     exec_output += PredOpExecute.subst(vmovRegSIop);
 
     vmovRegDCode = vfpEnabledCheckCode + '''
-        FpDestP0.uw = FpOp1P0.uw;
-        FpDestP1.uw = FpOp1P1.uw;
+        FpDestP0_uw = FpOp1P0_uw;
+        FpDestP1_uw = FpOp1P1_uw;
     '''
     vmovRegDIop = InstObjParams("vmov", "VmovRegD", "FpRegRegOp",
                                 { "code": vmovRegDCode,
@@ -310,10 +310,10 @@ let {{
     exec_output += PredOpExecute.subst(vmovRegDIop);
 
     vmovRegQCode = vfpEnabledCheckCode + '''
-        FpDestP0.uw = FpOp1P0.uw;
-        FpDestP1.uw = FpOp1P1.uw;
-        FpDestP2.uw = FpOp1P2.uw;
-        FpDestP3.uw = FpOp1P3.uw;
+        FpDestP0_uw = FpOp1P0_uw;
+        FpDestP1_uw = FpOp1P1_uw;
+        FpDestP2_uw = FpOp1P2_uw;
+        FpDestP3_uw = FpOp1P3_uw;
     '''
     vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "FpRegRegOp",
                                 { "code": vmovRegQCode,
@@ -324,7 +324,7 @@ let {{
     exec_output += PredOpExecute.subst(vmovRegQIop);
 
     vmovCoreRegBCode = vfpEnabledCheckCode + '''
-        FpDest.uw = insertBits(FpDest.uw, imm * 8 + 7, imm * 8, Op1.ub);
+        FpDest_uw = insertBits(FpDest_uw, imm * 8 + 7, imm * 8, Op1_ub);
     '''
     vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "FpRegRegImmOp",
                                     { "code": vmovCoreRegBCode,
@@ -335,7 +335,7 @@ let {{
     exec_output += PredOpExecute.subst(vmovCoreRegBIop);
 
     vmovCoreRegHCode = vfpEnabledCheckCode + '''
-        FpDest.uw = insertBits(FpDest.uw, imm * 16 + 15, imm * 16, Op1.uh);
+        FpDest_uw = insertBits(FpDest_uw, imm * 16 + 15, imm * 16, Op1_uh);
     '''
     vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "FpRegRegImmOp",
                                     { "code": vmovCoreRegHCode,
@@ -346,7 +346,7 @@ let {{
     exec_output += PredOpExecute.subst(vmovCoreRegHIop);
 
     vmovCoreRegWCode = vfpEnabledCheckCode + '''
-        FpDest.uw = Op1.uw;
+        FpDest_uw = Op1_uw;
     '''
     vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "FpRegRegOp",
                                     { "code": vmovCoreRegWCode,
@@ -358,7 +358,7 @@ let {{
 
     vmovRegCoreUBCode = vfpEnabledCheckCode + '''
         assert(imm < 4);
-        Dest = bits(FpOp1.uw, imm * 8 + 7, imm * 8);
+        Dest = bits(FpOp1_uw, imm * 8 + 7, imm * 8);
     '''
     vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "FpRegRegImmOp",
                                      { "code": vmovRegCoreUBCode,
@@ -370,7 +370,7 @@ let {{
 
     vmovRegCoreUHCode = vfpEnabledCheckCode + '''
         assert(imm < 2);
-        Dest = bits(FpOp1.uw, imm * 16 + 15, imm * 16);
+        Dest = bits(FpOp1_uw, imm * 16 + 15, imm * 16);
     '''
     vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "FpRegRegImmOp",
                                      { "code": vmovRegCoreUHCode,
@@ -382,7 +382,7 @@ let {{
 
     vmovRegCoreSBCode = vfpEnabledCheckCode + '''
         assert(imm < 4);
-        Dest = sext<8>(bits(FpOp1.uw, imm * 8 + 7, imm * 8));
+        Dest = sext<8>(bits(FpOp1_uw, imm * 8 + 7, imm * 8));
     '''
     vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "FpRegRegImmOp",
                                      { "code": vmovRegCoreSBCode,
@@ -394,7 +394,7 @@ let {{
 
     vmovRegCoreSHCode = vfpEnabledCheckCode + '''
         assert(imm < 2);
-        Dest = sext<16>(bits(FpOp1.uw, imm * 16 + 15, imm * 16));
+        Dest = sext<16>(bits(FpOp1_uw, imm * 16 + 15, imm * 16));
     '''
     vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "FpRegRegImmOp",
                                      { "code": vmovRegCoreSHCode,
@@ -405,7 +405,7 @@ let {{
     exec_output += PredOpExecute.subst(vmovRegCoreSHIop);
 
     vmovRegCoreWCode = vfpEnabledCheckCode + '''
-        Dest = FpOp1.uw;
+        Dest = FpOp1_uw;
     '''
     vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "FpRegRegOp",
                                      { "code": vmovRegCoreWCode,
@@ -416,8 +416,8 @@ let {{
     exec_output += PredOpExecute.subst(vmovRegCoreWIop);
 
     vmov2Reg2CoreCode = vfpEnabledCheckCode + '''
-        FpDestP0.uw = Op1.uw;
-        FpDestP1.uw = Op2.uw;
+        FpDestP0_uw = Op1_uw;
+        FpDestP1_uw = Op2_uw;
     '''
     vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "FpRegRegRegOp",
                                      { "code": vmov2Reg2CoreCode,
@@ -428,8 +428,8 @@ let {{
     exec_output += PredOpExecute.subst(vmov2Reg2CoreIop);
 
     vmov2Core2RegCode = vfpEnabledCheckCode + '''
-        Dest.uw = FpOp2P0.uw;
-        Op1.uw = FpOp2P1.uw;
+        Dest_uw = FpOp2P0_uw;
+        Op1_uw = FpOp2P1_uw;
     '''
     vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "FpRegRegRegOp",
                                      { "code": vmov2Core2RegCode,
@@ -459,17 +459,17 @@ let {{
     doubleCode = vfpEnabledCheckCode + '''
         FPSCR fpscr = (FPSCR) FpscrExc;
         double dest = %(op)s;
-        FpDestP0.uw = dblLow(dest);
-        FpDestP1.uw = dblHi(dest);
+        FpDestP0_uw = dblLow(dest);
+        FpDestP1_uw = dblHi(dest);
         FpscrExc = fpscr;
     '''
     doubleBinOp = '''
-        binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),
-                        dbl(FpOp2P0.uw, FpOp2P1.uw),
+        binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw),
+                        dbl(FpOp2P0_uw, FpOp2P1_uw),
                         %(func)s, fpscr.fz, fpscr.dn, fpscr.rMode);
     '''
     doubleUnaryOp = '''
-        unaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), %(func)s,
+        unaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), %(func)s,
                 fpscr.fz, fpscr.rMode)
     '''
 
@@ -559,9 +559,9 @@ let {{
             exec_output += PredOpExecute.subst(iop)
 
     buildSimpleUnaryFpOp("vneg", "Vneg", "FpRegRegOp", "SimdFloatMiscOp",
-                         "-FpOp1", "-dbl(FpOp1P0.uw, FpOp1P1.uw)")
+                         "-FpOp1", "-dbl(FpOp1P0_uw, FpOp1P1_uw)")
     buildSimpleUnaryFpOp("vabs", "Vabs", "FpRegRegOp", "SimdFloatMiscOp",
-                         "fabsf(FpOp1)", "fabs(dbl(FpOp1P0.uw, FpOp1P1.uw))")
+                         "fabsf(FpOp1)", "fabs(dbl(FpOp1P0_uw, FpOp1P1_uw))")
 }};
 
 let {{
@@ -588,14 +588,14 @@ let {{
 
     vmlaDCode = vfpEnabledCheckCode + '''
         FPSCR fpscr = (FPSCR) FpscrExc;
-        double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),
-                                     dbl(FpOp2P0.uw, FpOp2P1.uw),
+        double mid = binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw),
+                                     dbl(FpOp2P0_uw, FpOp2P1_uw),
                                      fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode);
-        double dest = binaryOp(fpscr, dbl(FpDestP0.uw, FpDestP1.uw),
+        double dest = binaryOp(fpscr, dbl(FpDestP0_uw, FpDestP1_uw),
                                       mid, fpAddD, fpscr.fz,
                                       fpscr.dn, fpscr.rMode);
-        FpDestP0.uw = dblLow(dest);
-        FpDestP1.uw = dblHi(dest);
+        FpDestP0_uw = dblLow(dest);
+        FpDestP1_uw = dblHi(dest);
         FpscrExc = fpscr;
     '''
     vmlaDIop = InstObjParams("vmlad", "VmlaD", "FpRegRegRegOp",
@@ -624,14 +624,14 @@ let {{
 
     vmlsDCode = vfpEnabledCheckCode + '''
         FPSCR fpscr = (FPSCR) FpscrExc;
-        double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),
-                                     dbl(FpOp2P0.uw, FpOp2P1.uw),
+        double mid = binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw),
+                                     dbl(FpOp2P0_uw, FpOp2P1_uw),
                                      fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode);
-        double dest = binaryOp(fpscr, dbl(FpDestP0.uw, FpDestP1.uw),
+        double dest = binaryOp(fpscr, dbl(FpDestP0_uw, FpDestP1_uw),
                                       -mid, fpAddD, fpscr.fz,
                                       fpscr.dn, fpscr.rMode);
-        FpDestP0.uw = dblLow(dest);
-        FpDestP1.uw = dblHi(dest);
+        FpDestP0_uw = dblLow(dest);
+        FpDestP1_uw = dblHi(dest);
         FpscrExc = fpscr;
     '''
     vmlsDIop = InstObjParams("vmlsd", "VmlsD", "FpRegRegRegOp",
@@ -660,14 +660,14 @@ let {{
 
     vnmlaDCode = vfpEnabledCheckCode + '''
         FPSCR fpscr = (FPSCR) FpscrExc;
-        double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),
-                                     dbl(FpOp2P0.uw, FpOp2P1.uw),
+        double mid = binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw),
+                                     dbl(FpOp2P0_uw, FpOp2P1_uw),
                                      fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode);
-        double dest = binaryOp(fpscr, -dbl(FpDestP0.uw, FpDestP1.uw),
+        double dest = binaryOp(fpscr, -dbl(FpDestP0_uw, FpDestP1_uw),
                                       -mid, fpAddD, fpscr.fz,
                                       fpscr.dn, fpscr.rMode);
-        FpDestP0.uw = dblLow(dest);
-        FpDestP1.uw = dblHi(dest);
+        FpDestP0_uw = dblLow(dest);
+        FpDestP1_uw = dblHi(dest);
         FpscrExc = fpscr;
     '''
     vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "FpRegRegRegOp",
@@ -696,14 +696,14 @@ let {{
 
     vnmlsDCode = vfpEnabledCheckCode + '''
         FPSCR fpscr = (FPSCR) FpscrExc;
-        double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),
-                                     dbl(FpOp2P0.uw, FpOp2P1.uw),
+        double mid = binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw),
+                                     dbl(FpOp2P0_uw, FpOp2P1_uw),
                                      fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode);
-        double dest = binaryOp(fpscr, -dbl(FpDestP0.uw, FpDestP1.uw),
+        double dest = binaryOp(fpscr, -dbl(FpDestP0_uw, FpDestP1_uw),
                                       mid, fpAddD, fpscr.fz,
                                       fpscr.dn, fpscr.rMode);
-        FpDestP0.uw = dblLow(dest);
-        FpDestP1.uw = dblHi(dest);
+        FpDestP0_uw = dblLow(dest);
+        FpDestP1_uw = dblHi(dest);
         FpscrExc = fpscr;
     '''
     vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "FpRegRegRegOp",
@@ -730,12 +730,12 @@ let {{
 
     vnmulDCode = vfpEnabledCheckCode + '''
         FPSCR fpscr = (FPSCR) FpscrExc;
-        double dest = -binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),
-                                       dbl(FpOp2P0.uw, FpOp2P1.uw),
+        double dest = -binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw),
+                                       dbl(FpOp2P0_uw, FpOp2P1_uw),
                                        fpMulD, fpscr.fz, fpscr.dn,
                                        fpscr.rMode);
-        FpDestP0.uw = dblLow(dest);
-        FpDestP1.uw = dblHi(dest);
+        FpDestP0_uw = dblLow(dest);
+        FpDestP1_uw = dblHi(dest);
         FpscrExc = fpscr;
     '''
     vnmulDIop = InstObjParams("vnmuld", "VnmulD", "FpRegRegRegOp",
@@ -756,8 +756,8 @@ let {{
     vcvtUIntFpSCode = vfpEnabledCheckCode + '''
         FPSCR fpscr = (FPSCR) FpscrExc;
         VfpSavedState state = prepFpState(fpscr.rMode);
-        __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw));
-        FpDest = FpOp1.uw;
+        __asm__ __volatile__("" : "=m" (FpOp1_uw) : "m" (FpOp1_uw));
+        FpDest = FpOp1_uw;
         __asm__ __volatile__("" :: "m" (FpDest));
         finishVfp(fpscr, state, fpscr.fz);
         FpscrExc = fpscr;
@@ -773,12 +773,12 @@ let {{
     vcvtUIntFpDCode = vfpEnabledCheckCode + '''
         FPSCR fpscr = (FPSCR) FpscrExc;
         VfpSavedState state = prepFpState(fpscr.rMode);
-        __asm__ __volatile__("" : "=m" (FpOp1P0.uw) : "m" (FpOp1P0.uw));
-        double cDest = (uint64_t)FpOp1P0.uw;
+        __asm__ __volatile__("" : "=m" (FpOp1P0_uw) : "m" (FpOp1P0_uw));
+        double cDest = (uint64_t)FpOp1P0_uw;
         __asm__ __volatile__("" :: "m" (cDest));
         finishVfp(fpscr, state, fpscr.fz);
-        FpDestP0.uw = dblLow(cDest);
-        FpDestP1.uw = dblHi(cDest);
+        FpDestP0_uw = dblLow(cDest);
+        FpDestP1_uw = dblHi(cDest);
         FpscrExc = fpscr;
     '''
     vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "FpRegRegOp",
@@ -792,8 +792,8 @@ let {{
     vcvtSIntFpSCode = vfpEnabledCheckCode + '''
         FPSCR fpscr = (FPSCR) FpscrExc;
         VfpSavedState state = prepFpState(fpscr.rMode);
-        __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw));
-        FpDest = FpOp1.sw;
+        __asm__ __volatile__("" : "=m" (FpOp1_sw) : "m" (FpOp1_sw));
+        FpDest = FpOp1_sw;
         __asm__ __volatile__("" :: "m" (FpDest));
         finishVfp(fpscr, state, fpscr.fz);
         FpscrExc = fpscr;
@@ -809,12 +809,12 @@ let {{
     vcvtSIntFpDCode = vfpEnabledCheckCode + '''
         FPSCR fpscr = (FPSCR) FpscrExc;
         VfpSavedState state = prepFpState(fpscr.rMode);
-        __asm__ __volatile__("" : "=m" (FpOp1P0.sw) : "m" (FpOp1P0.sw));
-        double cDest = FpOp1P0.sw;
+        __asm__ __volatile__("" : "=m" (FpOp1P0_sw) : "m" (FpOp1P0_sw));
+        double cDest = FpOp1P0_sw;
         __asm__ __volatile__("" :: "m" (cDest));
         finishVfp(fpscr, state, fpscr.fz);
-        FpDestP0.uw = dblLow(cDest);
-        FpDestP1.uw = dblHi(cDest);
+        FpDestP0_uw = dblLow(cDest);
+        FpDestP1_uw = dblHi(cDest);
         FpscrExc = fpscr;
     '''
     vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "FpRegRegOp",
@@ -830,8 +830,8 @@ let {{
         VfpSavedState state = prepFpState(fpscr.rMode);
         vfpFlushToZero(fpscr, FpOp1);
         __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
-        FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0, false);
-        __asm__ __volatile__("" :: "m" (FpDest.uw));
+        FpDest_uw = vfpFpSToFixed(FpOp1, false, false, 0, false);
+        __asm__ __volatile__("" :: "m" (FpDest_uw));
         finishVfp(fpscr, state, fpscr.fz);
         FpscrExc = fpscr;
     '''
@@ -845,14 +845,14 @@ let {{
 
     vcvtFpUIntDRCode = vfpEnabledCheckCode + '''
         FPSCR fpscr = (FPSCR) FpscrExc;
-        double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
+        double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw);
         vfpFlushToZero(fpscr, cOp1);
         VfpSavedState state = prepFpState(fpscr.rMode);
         __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
         uint64_t result = vfpFpDToFixed(cOp1, false, false, 0, false);
         __asm__ __volatile__("" :: "m" (result));
         finishVfp(fpscr, state, fpscr.fz);
-        FpDestP0.uw = result;
+        FpDestP0_uw = result;
         FpscrExc = fpscr;
     '''
     vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "FpRegRegOp",
@@ -868,8 +868,8 @@ let {{
         VfpSavedState state = prepFpState(fpscr.rMode);
         vfpFlushToZero(fpscr, FpOp1);
         __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
-        FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0, false);
-        __asm__ __volatile__("" :: "m" (FpDest.sw));
+        FpDest_sw = vfpFpSToFixed(FpOp1, true, false, 0, false);
+        __asm__ __volatile__("" :: "m" (FpDest_sw));
         finishVfp(fpscr, state, fpscr.fz);
         FpscrExc = fpscr;
     '''
@@ -883,14 +883,14 @@ let {{
 
     vcvtFpSIntDRCode = vfpEnabledCheckCode + '''
         FPSCR fpscr = (FPSCR) FpscrExc;
-        double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
+        double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw);
         vfpFlushToZero(fpscr, cOp1);
         VfpSavedState state = prepFpState(fpscr.rMode);
         __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
         int64_t result = vfpFpDToFixed(cOp1, true, false, 0, false);
         __asm__ __volatile__("" :: "m" (result));
         finishVfp(fpscr, state, fpscr.fz);
-        FpDestP0.uw = result;
+        FpDestP0_uw = result;
         FpscrExc = fpscr;
     '''
     vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp",
@@ -907,8 +907,8 @@ let {{
         VfpSavedState state = prepFpState(fpscr.rMode);
         fesetround(FeRoundZero);
         __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
-        FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0);
-        __asm__ __volatile__("" :: "m" (FpDest.uw));
+        FpDest_uw = vfpFpSToFixed(FpOp1, false, false, 0);
+        __asm__ __volatile__("" :: "m" (FpDest_uw));
         finishVfp(fpscr, state, fpscr.fz);
         FpscrExc = fpscr;
     '''
@@ -922,7 +922,7 @@ let {{
 
     vcvtFpUIntDCode = vfpEnabledCheckCode + '''
         FPSCR fpscr = (FPSCR) FpscrExc;
-        double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
+        double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw);
         vfpFlushToZero(fpscr, cOp1);
         VfpSavedState state = prepFpState(fpscr.rMode);
         fesetround(FeRoundZero);
@@ -930,7 +930,7 @@ let {{
         uint64_t result = vfpFpDToFixed(cOp1, false, false, 0);
         __asm__ __volatile__("" :: "m" (result));
         finishVfp(fpscr, state, fpscr.fz);
-        FpDestP0.uw = result;
+        FpDestP0_uw = result;
         FpscrExc = fpscr;
     '''
     vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "FpRegRegOp",
@@ -947,8 +947,8 @@ let {{
         VfpSavedState state = prepFpState(fpscr.rMode);
         fesetround(FeRoundZero);
         __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
-        FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0);
-        __asm__ __volatile__("" :: "m" (FpDest.sw));
+        FpDest_sw = vfpFpSToFixed(FpOp1, true, false, 0);
+        __asm__ __volatile__("" :: "m" (FpDest_sw));
         finishVfp(fpscr, state, fpscr.fz);
         FpscrExc = fpscr;
     '''
@@ -962,7 +962,7 @@ let {{
 
     vcvtFpSIntDCode = vfpEnabledCheckCode + '''
         FPSCR fpscr = (FPSCR) FpscrExc;
-        double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
+        double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw);
         vfpFlushToZero(fpscr, cOp1);
         VfpSavedState state = prepFpState(fpscr.rMode);
         fesetround(FeRoundZero);
@@ -970,7 +970,7 @@ let {{
         int64_t result = vfpFpDToFixed(cOp1, true, false, 0);
         __asm__ __volatile__("" :: "m" (result));
         finishVfp(fpscr, state, fpscr.fz);
-        FpDestP0.uw = result;
+        FpDestP0_uw = result;
         FpscrExc = fpscr;
     '''
     vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "FpRegRegOp",
@@ -989,8 +989,8 @@ let {{
         double cDest = fixFpSFpDDest(FpscrExc, FpOp1);
         __asm__ __volatile__("" :: "m" (cDest));
         finishVfp(fpscr, state, fpscr.fz);
-        FpDestP0.uw = dblLow(cDest);
-        FpDestP1.uw = dblHi(cDest);
+        FpDestP0_uw = dblLow(cDest);
+        FpDestP1_uw = dblHi(cDest);
         FpscrExc = fpscr;
     '''
     vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "FpRegRegOp",
@@ -1003,7 +1003,7 @@ let {{
 
     vcvtFpDFpSCode = vfpEnabledCheckCode + '''
         FPSCR fpscr = (FPSCR) FpscrExc;
-        double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
+        double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw);
         vfpFlushToZero(fpscr, cOp1);
         VfpSavedState state = prepFpState(fpscr.rMode);
         __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
@@ -1061,12 +1061,12 @@ let {{
         FPSCR fpscr = (FPSCR) FpscrExc;
         vfpFlushToZero(fpscr, FpOp1);
         VfpSavedState state = prepFpState(fpscr.rMode);
-        __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest.uw)
-                                : "m" (FpOp1), "m" (FpDest.uw));
-        FpDest.uw = insertBits(FpDest.uw, 31, 16,,
+        __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest_uw)
+                                : "m" (FpOp1), "m" (FpDest_uw));
+        FpDest_uw = insertBits(FpDest_uw, 31, 16,,
                                vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn,
                                fpscr.rMode, fpscr.ahp, FpOp1));
-        __asm__ __volatile__("" :: "m" (FpDest.uw));
+        __asm__ __volatile__("" :: "m" (FpDest_uw));
         finishVfp(fpscr, state, fpscr.fz);
         FpscrExc = fpscr;
     '''
@@ -1082,12 +1082,12 @@ let {{
         FPSCR fpscr = (FPSCR) FpscrExc;
         vfpFlushToZero(fpscr, FpOp1);
         VfpSavedState state = prepFpState(fpscr.rMode);
-        __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest.uw)
-                                : "m" (FpOp1), "m" (FpDest.uw));
-        FpDest.uw = insertBits(FpDest.uw, 15, 0,
+        __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest_uw)
+                                : "m" (FpOp1), "m" (FpDest_uw));
+        FpDest_uw = insertBits(FpDest_uw, 15, 0,
                                vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn,
                                fpscr.rMode, fpscr.ahp, FpOp1));
-        __asm__ __volatile__("" :: "m" (FpDest.uw));
+        __asm__ __volatile__("" :: "m" (FpDest_uw));
         finishVfp(fpscr, state, fpscr.fz);
         FpscrExc = fpscr;
     '''
@@ -1130,8 +1130,8 @@ let {{
     exec_output += PredOpExecute.subst(vcmpSIop);
 
     vcmpDCode = vfpEnabledCheckCode + '''
-        double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
-        double cDest = dbl(FpDestP0.uw, FpDestP1.uw);
+        double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw);
+        double cDest = dbl(FpDestP0_uw, FpDestP1_uw);
         FPSCR fpscr = (FPSCR) FpscrExc;
         vfpFlushToZero(fpscr, cDest, cOp1);
         if (cDest == cOp1) {
@@ -1194,7 +1194,7 @@ let {{
     vcmpZeroDCode = vfpEnabledCheckCode + '''
         // This only handles imm == 0 for now.
         assert(imm == 0);
-        double cDest = dbl(FpDestP0.uw, FpDestP1.uw);
+        double cDest = dbl(FpDestP0_uw, FpDestP1_uw);
         FPSCR fpscr = (FPSCR) FpscrExc;
         vfpFlushToZero(fpscr, cDest);
         if (cDest == imm) {
@@ -1247,8 +1247,8 @@ let {{
     exec_output += PredOpExecute.subst(vcmpeSIop);
 
     vcmpeDCode = vfpEnabledCheckCode + '''
-        double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
-        double cDest = dbl(FpDestP0.uw, FpDestP1.uw);
+        double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw);
+        double cDest = dbl(FpDestP0_uw, FpDestP1_uw);
         FPSCR fpscr = (FPSCR) FpscrExc;
         vfpFlushToZero(fpscr, cDest, cOp1);
         if (cDest == cOp1) {
@@ -1297,7 +1297,7 @@ let {{
     exec_output += PredOpExecute.subst(vcmpeZeroSIop);
 
     vcmpeZeroDCode = vfpEnabledCheckCode + '''
-        double cDest = dbl(FpDestP0.uw, FpDestP1.uw);
+        double cDest = dbl(FpDestP0_uw, FpDestP1_uw);
         FPSCR fpscr = (FPSCR) FpscrExc;
         vfpFlushToZero(fpscr, cDest);
         if (cDest == imm) {
@@ -1333,8 +1333,8 @@ let {{
         vfpFlushToZero(fpscr, FpOp1);
         VfpSavedState state = prepFpState(fpscr.rMode);
         __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
-        FpDest.sw = vfpFpSToFixed(FpOp1, true, false, imm);
-        __asm__ __volatile__("" :: "m" (FpDest.sw));
+        FpDest_sw = vfpFpSToFixed(FpOp1, true, false, imm);
+        __asm__ __volatile__("" :: "m" (FpDest_sw));
         finishVfp(fpscr, state, fpscr.fz);
         FpscrExc = fpscr;
     '''
@@ -1348,15 +1348,15 @@ let {{
 
     vcvtFpSFixedDCode = vfpEnabledCheckCode + '''
         FPSCR fpscr = (FPSCR) FpscrExc;
-        double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
+        double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw);
         vfpFlushToZero(fpscr, cOp1);
         VfpSavedState state = prepFpState(fpscr.rMode);
         __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
         uint64_t mid = vfpFpDToFixed(cOp1, true, false, imm);
         __asm__ __volatile__("" :: "m" (mid));
         finishVfp(fpscr, state, fpscr.fz);
-        FpDestP0.uw = mid;
-        FpDestP1.uw = mid >> 32;
+        FpDestP0_uw = mid;
+        FpDestP1_uw = mid >> 32;
         FpscrExc = fpscr;
     '''
     vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "FpRegRegImmOp",
@@ -1372,8 +1372,8 @@ let {{
         vfpFlushToZero(fpscr, FpOp1);
         VfpSavedState state = prepFpState(fpscr.rMode);
         __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
-        FpDest.uw = vfpFpSToFixed(FpOp1, false, false, imm);
-        __asm__ __volatile__("" :: "m" (FpDest.uw));
+        FpDest_uw = vfpFpSToFixed(FpOp1, false, false, imm);
+        __asm__ __volatile__("" :: "m" (FpDest_uw));
         finishVfp(fpscr, state, fpscr.fz);
         FpscrExc = fpscr;
     '''
@@ -1387,15 +1387,15 @@ let {{
 
     vcvtFpUFixedDCode = vfpEnabledCheckCode + '''
         FPSCR fpscr = (FPSCR) FpscrExc;
-        double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
+        double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw);
         vfpFlushToZero(fpscr, cOp1);
         VfpSavedState state = prepFpState(fpscr.rMode);
         __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
         uint64_t mid = vfpFpDToFixed(cOp1, false, false, imm);
         __asm__ __volatile__("" :: "m" (mid));
         finishVfp(fpscr, state, fpscr.fz);
-        FpDestP0.uw = mid;
-        FpDestP1.uw = mid >> 32;
+        FpDestP0_uw = mid;
+        FpDestP1_uw = mid >> 32;
         FpscrExc = fpscr;
     '''
     vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "FpRegRegImmOp",
@@ -1409,8 +1409,8 @@ let {{
     vcvtSFixedFpSCode = vfpEnabledCheckCode + '''
         FPSCR fpscr = (FPSCR) FpscrExc;
         VfpSavedState state = prepFpState(fpscr.rMode);
-        __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw));
-        FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.sw, false, imm);
+        __asm__ __volatile__("" : "=m" (FpOp1_sw) : "m" (FpOp1_sw));
+        FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_sw, false, imm);
         __asm__ __volatile__("" :: "m" (FpDest));
         finishVfp(fpscr, state, fpscr.fz);
         FpscrExc = fpscr;
@@ -1425,14 +1425,14 @@ let {{
 
     vcvtSFixedFpDCode = vfpEnabledCheckCode + '''
         FPSCR fpscr = (FPSCR) FpscrExc;
-        uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
+        uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32));
         VfpSavedState state = prepFpState(fpscr.rMode);
         __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
         double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, false, imm);
         __asm__ __volatile__("" :: "m" (cDest));
         finishVfp(fpscr, state, fpscr.fz);
-        FpDestP0.uw = dblLow(cDest);
-        FpDestP1.uw = dblHi(cDest);
+        FpDestP0_uw = dblLow(cDest);
+        FpDestP1_uw = dblHi(cDest);
         FpscrExc = fpscr;
     '''
     vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "FpRegRegImmOp",
@@ -1446,8 +1446,8 @@ let {{
     vcvtUFixedFpSCode = vfpEnabledCheckCode + '''
         FPSCR fpscr = (FPSCR) FpscrExc;
         VfpSavedState state = prepFpState(fpscr.rMode);
-        __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw));
-        FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.uw, false, imm);
+        __asm__ __volatile__("" : "=m" (FpOp1_uw) : "m" (FpOp1_uw));
+        FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_uw, false, imm);
         __asm__ __volatile__("" :: "m" (FpDest));
         finishVfp(fpscr, state, fpscr.fz);
         FpscrExc = fpscr;
@@ -1462,14 +1462,14 @@ let {{
 
     vcvtUFixedFpDCode = vfpEnabledCheckCode + '''
         FPSCR fpscr = (FPSCR) FpscrExc;
-        uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
+        uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32));
         VfpSavedState state = prepFpState(fpscr.rMode);
         __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
         double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, false, imm);
         __asm__ __volatile__("" :: "m" (cDest));
         finishVfp(fpscr, state, fpscr.fz);
-        FpDestP0.uw = dblLow(cDest);
-        FpDestP1.uw = dblHi(cDest);
+        FpDestP0_uw = dblLow(cDest);
+        FpDestP1_uw = dblHi(cDest);
         FpscrExc = fpscr;
     '''
     vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "FpRegRegImmOp",
@@ -1485,8 +1485,8 @@ let {{
         vfpFlushToZero(fpscr, FpOp1);
         VfpSavedState state = prepFpState(fpscr.rMode);
         __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
-        FpDest.sh = vfpFpSToFixed(FpOp1, true, true, imm);
-        __asm__ __volatile__("" :: "m" (FpDest.sh));
+        FpDest_sh = vfpFpSToFixed(FpOp1, true, true, imm);
+        __asm__ __volatile__("" :: "m" (FpDest_sh));
         finishVfp(fpscr, state, fpscr.fz);
         FpscrExc = fpscr;
     '''
@@ -1501,15 +1501,15 @@ let {{
 
     vcvtFpSHFixedDCode = vfpEnabledCheckCode + '''
         FPSCR fpscr = (FPSCR) FpscrExc;
-        double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
+        double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw);
         vfpFlushToZero(fpscr, cOp1);
         VfpSavedState state = prepFpState(fpscr.rMode);
         __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
         uint64_t result = vfpFpDToFixed(cOp1, true, true, imm);
         __asm__ __volatile__("" :: "m" (result));
         finishVfp(fpscr, state, fpscr.fz);
-        FpDestP0.uw = result;
-        FpDestP1.uw = result >> 32;
+        FpDestP0_uw = result;
+        FpDestP1_uw = result >> 32;
         FpscrExc = fpscr;
     '''
     vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD",
@@ -1526,8 +1526,8 @@ let {{
         vfpFlushToZero(fpscr, FpOp1);
         VfpSavedState state = prepFpState(fpscr.rMode);
         __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
-        FpDest.uh = vfpFpSToFixed(FpOp1, false, true, imm);
-        __asm__ __volatile__("" :: "m" (FpDest.uh));
+        FpDest_uh = vfpFpSToFixed(FpOp1, false, true, imm);
+        __asm__ __volatile__("" :: "m" (FpDest_uh));
         finishVfp(fpscr, state, fpscr.fz);
         FpscrExc = fpscr;
     '''
@@ -1542,15 +1542,15 @@ let {{
 
     vcvtFpUHFixedDCode = vfpEnabledCheckCode + '''
         FPSCR fpscr = (FPSCR) FpscrExc;
-        double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
+        double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw);
         vfpFlushToZero(fpscr, cOp1);
         VfpSavedState state = prepFpState(fpscr.rMode);
         __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
         uint64_t mid = vfpFpDToFixed(cOp1, false, true, imm);
         __asm__ __volatile__("" :: "m" (mid));
         finishVfp(fpscr, state, fpscr.fz);
-        FpDestP0.uw = mid;
-        FpDestP1.uw = mid >> 32;
+        FpDestP0_uw = mid;
+        FpDestP1_uw = mid >> 32;
         FpscrExc = fpscr;
     '''
     vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD",
@@ -1565,8 +1565,8 @@ let {{
     vcvtSHFixedFpSCode = vfpEnabledCheckCode + '''
         FPSCR fpscr = (FPSCR) FpscrExc;
         VfpSavedState state = prepFpState(fpscr.rMode);
-        __asm__ __volatile__("" : "=m" (FpOp1.sh) : "m" (FpOp1.sh));
-        FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.sh, true, imm);
+        __asm__ __volatile__("" : "=m" (FpOp1_sh) : "m" (FpOp1_sh));
+        FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_sh, true, imm);
         __asm__ __volatile__("" :: "m" (FpDest));
         finishVfp(fpscr, state, fpscr.fz);
         FpscrExc = fpscr;
@@ -1582,14 +1582,14 @@ let {{
 
     vcvtSHFixedFpDCode = vfpEnabledCheckCode + '''
         FPSCR fpscr = (FPSCR) FpscrExc;
-        uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
+        uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32));
         VfpSavedState state = prepFpState(fpscr.rMode);
         __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
         double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, true, imm);
         __asm__ __volatile__("" :: "m" (cDest));
         finishVfp(fpscr, state, fpscr.fz);
-        FpDestP0.uw = dblLow(cDest);
-        FpDestP1.uw = dblHi(cDest);
+        FpDestP0_uw = dblLow(cDest);
+        FpDestP1_uw = dblHi(cDest);
         FpscrExc = fpscr;
     '''
     vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD",
@@ -1604,8 +1604,8 @@ let {{
     vcvtUHFixedFpSCode = vfpEnabledCheckCode + '''
         FPSCR fpscr = (FPSCR) FpscrExc;
         VfpSavedState state = prepFpState(fpscr.rMode);
-        __asm__ __volatile__("" : "=m" (FpOp1.uh) : "m" (FpOp1.uh));
-        FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.uh, true, imm);
+        __asm__ __volatile__("" : "=m" (FpOp1_uh) : "m" (FpOp1_uh));
+        FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_uh, true, imm);
         __asm__ __volatile__("" :: "m" (FpDest));
         finishVfp(fpscr, state, fpscr.fz);
         FpscrExc = fpscr;
@@ -1621,14 +1621,14 @@ let {{
 
     vcvtUHFixedFpDCode = vfpEnabledCheckCode + '''
         FPSCR fpscr = (FPSCR) FpscrExc;
-        uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
+        uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32));
         VfpSavedState state = prepFpState(fpscr.rMode);
         __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
         double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, true, imm);
         __asm__ __volatile__("" :: "m" (cDest));
         finishVfp(fpscr, state, fpscr.fz);
-        FpDestP0.uw = dblLow(cDest);
-        FpDestP1.uw = dblHi(cDest);
+        FpDestP0_uw = dblLow(cDest);
+        FpDestP1_uw = dblHi(cDest);
         FpscrExc = fpscr;
     '''
     vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD",
diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa
index 4c8bfd612..f599fa4b9 100644
--- a/src/arch/arm/isa/insts/ldr.isa
+++ b/src/arch/arm/isa/insts/ldr.isa
@@ -111,8 +111,8 @@ let {{
             cpsr.v = CondCodesV;
             cpsr.ge = CondCodesGE;
             URc = cpsr;
-            URa = cSwap<uint32_t>(Mem.ud, cpsr.e);
-            URb = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e);
+            URa = cSwap<uint32_t>(Mem_ud, cpsr.e);
+            URb = cSwap<uint32_t>(Mem_ud >> 32, cpsr.e);
             '''
             self.codeBlobs["memacc_code"] = accCode
 
@@ -196,7 +196,7 @@ let {{
             if self.flavor == "dprefetch" or self.flavor == "iprefetch":
                 accCode = 'uint64_t temp = Mem%s; temp = temp;'
             elif self.flavor == "fp":
-                accCode = "FpDest.uw = cSwap(Mem%s, ((CPSR)Cpsr).e);\n"
+                accCode = "FpDest_uw = cSwap(Mem%s, ((CPSR)Cpsr).e);\n"
             else:
                 accCode = "IWDest = cSwap(Mem%s, ((CPSR)Cpsr).e);"
             accCode = accCode % buildMemSuffix(self.sign, self.size)
@@ -260,14 +260,14 @@ let {{
             if self.flavor != "fp":
                 accCode = '''
                 CPSR cpsr = Cpsr;
-                Dest = cSwap<uint32_t>(Mem.ud, cpsr.e);
-                Dest2 = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e);
+                Dest = cSwap<uint32_t>(Mem_ud, cpsr.e);
+                Dest2 = cSwap<uint32_t>(Mem_ud >> 32, cpsr.e);
                 '''
             else:
                 accCode = '''
-                uint64_t swappedMem = cSwap(Mem.ud, ((CPSR)Cpsr).e);
-                FpDest.uw = (uint32_t)swappedMem;
-                FpDest2.uw = (uint32_t)(swappedMem >> 32);
+                uint64_t swappedMem = cSwap(Mem_ud, ((CPSR)Cpsr).e);
+                FpDest_uw = (uint32_t)swappedMem;
+                FpDest2_uw = (uint32_t)(swappedMem >> 32);
                 '''
 
             self.codeBlobs["memacc_code"] = accCode
diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa
index d5b44cd05..815d4c258 100644
--- a/src/arch/arm/isa/insts/macromem.isa
+++ b/src/arch/arm/isa/insts/macromem.isa
@@ -47,7 +47,7 @@
 //
 
 let {{
-    microLdrUopCode = "IWRa = cSwap(Mem.uw, ((CPSR)Cpsr).e);"
+    microLdrUopCode = "IWRa = cSwap(Mem_uw, ((CPSR)Cpsr).e);"
     microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop',
                                    'MicroMemOp',
                                    {'memacc_code': microLdrUopCode,
@@ -55,7 +55,7 @@ let {{
                                     'predicate_test': predicateTest},
                                    ['IsMicroop'])
 
-    microLdrFpUopCode = "Fa.uw = cSwap(Mem.uw, ((CPSR)Cpsr).e);"
+    microLdrFpUopCode = "Fa_uw = cSwap(Mem_uw, ((CPSR)Cpsr).e);"
     microLdrFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrFpUop',
                                       'MicroMemOp',
                                       {'memacc_code': microLdrFpUopCode,
@@ -64,7 +64,7 @@ let {{
                                        'predicate_test': predicateTest},
                                       ['IsMicroop'])
 
-    microLdrDBFpUopCode = "Fa.uw = cSwap(Mem.uw, ((CPSR)Cpsr).e);"
+    microLdrDBFpUopCode = "Fa_uw = cSwap(Mem_uw, ((CPSR)Cpsr).e);"
     microLdrDBFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrDBFpUop',
                                       'MicroMemOp',
                                       {'memacc_code': microLdrFpUopCode,
@@ -75,7 +75,7 @@ let {{
                                        'predicate_test': predicateTest},
                                       ['IsMicroop'])
 
-    microLdrDTFpUopCode = "Fa.uw = cSwap(Mem.uw, ((CPSR)Cpsr).e);"
+    microLdrDTFpUopCode = "Fa_uw = cSwap(Mem_uw, ((CPSR)Cpsr).e);"
     microLdrDTFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrDTFpUop',
                                       'MicroMemOp',
                                       {'memacc_code': microLdrFpUopCode,
@@ -106,14 +106,14 @@ let {{
     microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop',
                                       'MicroMemOp',
                                       {'memacc_code':
-                                          microRetUopCode % 'Mem.uw',
+                                          microRetUopCode % 'Mem_uw',
                                        'ea_code':
                                           'EA = URb + (up ? imm : -imm);',
                                        'predicate_test': condPredicateTest},
                                       ['IsMicroop','IsNonSpeculative',
                                        'IsSerializeAfter'])
 
-    microStrUopCode = "Mem = cSwap(URa.uw, ((CPSR)Cpsr).e);"
+    microStrUopCode = "Mem = cSwap(URa_uw, ((CPSR)Cpsr).e);"
     microStrUopIop = InstObjParams('str_uop', 'MicroStrUop',
                                    'MicroMemOp',
                                    {'memacc_code': microStrUopCode,
@@ -122,7 +122,7 @@ let {{
                                     'predicate_test': predicateTest},
                                    ['IsMicroop'])
 
-    microStrFpUopCode = "Mem = cSwap(Fa.uw, ((CPSR)Cpsr).e);"
+    microStrFpUopCode = "Mem = cSwap(Fa_uw, ((CPSR)Cpsr).e);"
     microStrFpUopIop = InstObjParams('strfp_uop', 'MicroStrFpUop',
                                      'MicroMemOp',
                                      {'memacc_code': microStrFpUopCode,
@@ -132,7 +132,7 @@ let {{
                                       'predicate_test': predicateTest},
                                      ['IsMicroop'])
 
-    microStrDBFpUopCode = "Mem = cSwap(Fa.uw, ((CPSR)Cpsr).e);"
+    microStrDBFpUopCode = "Mem = cSwap(Fa_uw, ((CPSR)Cpsr).e);"
     microStrDBFpUopIop = InstObjParams('strfp_uop', 'MicroStrDBFpUop',
                                        'MicroMemOp',
                                        {'memacc_code': microStrFpUopCode,
@@ -144,7 +144,7 @@ let {{
                                         'predicate_test': predicateTest},
                                        ['IsMicroop'])
 
-    microStrDTFpUopCode = "Mem = cSwap(Fa.uw, ((CPSR)Cpsr).e);"
+    microStrDTFpUopCode = "Mem = cSwap(Fa_uw, ((CPSR)Cpsr).e);"
     microStrDTFpUopIop = InstObjParams('strfp_uop', 'MicroStrDTFpUop',
                                        'MicroMemOp',
                                        {'memacc_code': microStrFpUopCode,
@@ -214,14 +214,14 @@ let {{
             if reg == regs - 1:
                 mask = ' & mask(%d)' % (32 - 8 * (regs * 4 - size))
             regSetCode += '''
-            FpDestP%(reg)d.uw = gtoh(memUnion.floatRegBits[%(reg)d])%(mask)s;
+            FpDestP%(reg)d_uw = gtoh(memUnion.floatRegBits[%(reg)d])%(mask)s;
             ''' % { "reg" : reg, "mask" : mask }
 
         # Pull everything in from registers
         regGetCode = ''
         for reg in range(regs):
             regGetCode += '''
-            memUnion.floatRegBits[%(reg)d] = htog(FpDestP%(reg)d.uw);
+            memUnion.floatRegBits[%(reg)d] = htog(FpDestP%(reg)d_uw);
             ''' % { "reg" : reg }
 
         loadMemAccCode = convCode + regSetCode
@@ -293,12 +293,12 @@ let {{
         unloadConv = ''
         for dReg in range(dRegs):
             loadConv += '''
-                conv1.cRegs[%(sReg0)d] = htog(FpOp1P%(sReg0)d.uw);
-                conv1.cRegs[%(sReg1)d] = htog(FpOp1P%(sReg1)d.uw);
+                conv1.cRegs[%(sReg0)d] = htog(FpOp1P%(sReg0)d_uw);
+                conv1.cRegs[%(sReg1)d] = htog(FpOp1P%(sReg1)d_uw);
             ''' % { "sReg0" : (dReg * 2), "sReg1" : (dReg * 2 + 1) }
             unloadConv += '''
-                FpDestS%(dReg)dP0.uw = gtoh(conv2.cRegs[2 * %(dReg)d + 0]);
-                FpDestS%(dReg)dP1.uw = gtoh(conv2.cRegs[2 * %(dReg)d + 1]);
+                FpDestS%(dReg)dP0_uw = gtoh(conv2.cRegs[2 * %(dReg)d + 0]);
+                FpDestS%(dReg)dP1_uw = gtoh(conv2.cRegs[2 * %(dReg)d + 1]);
             ''' % { "dReg" : dReg }
         microDeintNeonCode = '''
             const unsigned dRegs = %(dRegs)d;
@@ -339,12 +339,12 @@ let {{
         unloadConv = ''
         for dReg in range(dRegs):
             loadConv += '''
-                conv1.cRegs[2 * %(dReg)d + 0] = htog(FpOp1S%(dReg)dP0.uw);
-                conv1.cRegs[2 * %(dReg)d + 1] = htog(FpOp1S%(dReg)dP1.uw);
+                conv1.cRegs[2 * %(dReg)d + 0] = htog(FpOp1S%(dReg)dP0_uw);
+                conv1.cRegs[2 * %(dReg)d + 1] = htog(FpOp1S%(dReg)dP1_uw);
             ''' % { "dReg" : dReg }
             unloadConv += '''
-                FpDestP%(sReg0)d.uw = gtoh(conv2.cRegs[%(sReg0)d]);
-                FpDestP%(sReg1)d.uw = gtoh(conv2.cRegs[%(sReg1)d]);
+                FpDestP%(sReg0)d_uw = gtoh(conv2.cRegs[%(sReg0)d]);
+                FpDestP%(sReg1)d_uw = gtoh(conv2.cRegs[%(sReg1)d]);
             ''' % { "sReg0" : (dReg * 2), "sReg1" : (dReg * 2 + 1) }
         microInterNeonCode = '''
             const unsigned dRegs = %(dRegs)d;
@@ -405,8 +405,8 @@ let {{
         baseLoadRegs = ''
         for reg in range(sRegs):
             baseLoadRegs += '''
-                sourceRegs.fRegs[%(reg0)d] = htog(FpOp1P%(reg0)d.uw);
-                sourceRegs.fRegs[%(reg1)d] = htog(FpOp1P%(reg1)d.uw);
+                sourceRegs.fRegs[%(reg0)d] = htog(FpOp1P%(reg0)d_uw);
+                sourceRegs.fRegs[%(reg1)d] = htog(FpOp1P%(reg1)d_uw);
             ''' % { "reg0" : (2 * reg + 0),
                     "reg1" : (2 * reg + 1) }
         for dRegs in range(sRegs, 5):
@@ -414,12 +414,12 @@ let {{
             loadRegs = baseLoadRegs
             for reg in range(dRegs):
                 loadRegs += '''
-                    destRegs[%(reg)d].fRegs[0] = htog(FpDestS%(reg)dP0.uw);
-                    destRegs[%(reg)d].fRegs[1] = htog(FpDestS%(reg)dP1.uw);
+                    destRegs[%(reg)d].fRegs[0] = htog(FpDestS%(reg)dP0_uw);
+                    destRegs[%(reg)d].fRegs[1] = htog(FpDestS%(reg)dP1_uw);
                 ''' % { "reg" : reg }
                 unloadRegs += '''
-                    FpDestS%(reg)dP0.uw = gtoh(destRegs[%(reg)d].fRegs[0]);
-                    FpDestS%(reg)dP1.uw = gtoh(destRegs[%(reg)d].fRegs[1]);
+                    FpDestS%(reg)dP0_uw = gtoh(destRegs[%(reg)d].fRegs[0]);
+                    FpDestS%(reg)dP1_uw = gtoh(destRegs[%(reg)d].fRegs[1]);
                 ''' % { "reg" : reg }
             microUnpackNeonCode = '''
             const unsigned perDReg = (2 * sizeof(FloatRegBits)) /
@@ -460,16 +460,16 @@ let {{
         loadRegs = ''
         for reg in range(sRegs):
             loadRegs += '''
-                sourceRegs.fRegs[%(reg0)d] = htog(FpOp1P%(reg0)d.uw);
-                sourceRegs.fRegs[%(reg1)d] = htog(FpOp1P%(reg1)d.uw);
+                sourceRegs.fRegs[%(reg0)d] = htog(FpOp1P%(reg0)d_uw);
+                sourceRegs.fRegs[%(reg1)d] = htog(FpOp1P%(reg1)d_uw);
             ''' % { "reg0" : (2 * reg + 0),
                     "reg1" : (2 * reg + 1) }
         for dRegs in range(sRegs, 5):
             unloadRegs = ''
             for reg in range(dRegs):
                 unloadRegs += '''
-                    FpDestS%(reg)dP0.uw = gtoh(destRegs[%(reg)d].fRegs[0]);
-                    FpDestS%(reg)dP1.uw = gtoh(destRegs[%(reg)d].fRegs[1]);
+                    FpDestS%(reg)dP0_uw = gtoh(destRegs[%(reg)d].fRegs[0]);
+                    FpDestS%(reg)dP1_uw = gtoh(destRegs[%(reg)d].fRegs[1]);
                 ''' % { "reg" : reg }
             microUnpackAllNeonCode = '''
             const unsigned perDReg = (2 * sizeof(FloatRegBits)) /
@@ -511,16 +511,16 @@ let {{
         unloadRegs = ''
         for reg in range(dRegs):
             unloadRegs += '''
-                FpDestP%(reg0)d.uw = gtoh(destRegs.fRegs[%(reg0)d]);
-                FpDestP%(reg1)d.uw = gtoh(destRegs.fRegs[%(reg1)d]);
+                FpDestP%(reg0)d_uw = gtoh(destRegs.fRegs[%(reg0)d]);
+                FpDestP%(reg1)d_uw = gtoh(destRegs.fRegs[%(reg1)d]);
             ''' % { "reg0" : (2 * reg + 0),
                     "reg1" : (2 * reg + 1) }
         for sRegs in range(dRegs, 5):
             loadRegs = ''
             for reg in range(sRegs):
                 loadRegs += '''
-                    sourceRegs[%(reg)d].fRegs[0] = htog(FpOp1S%(reg)dP0.uw);
-                    sourceRegs[%(reg)d].fRegs[1] = htog(FpOp1S%(reg)dP1.uw);
+                    sourceRegs[%(reg)d].fRegs[0] = htog(FpOp1S%(reg)dP0_uw);
+                    sourceRegs[%(reg)d].fRegs[1] = htog(FpOp1S%(reg)dP1_uw);
                 ''' % { "reg" : reg }
             microPackNeonCode = '''
             const unsigned perDReg = (2 * sizeof(FloatRegBits)) /
diff --git a/src/arch/arm/isa/insts/mem.isa b/src/arch/arm/isa/insts/mem.isa
index fb09eacb6..c39f1b14f 100644
--- a/src/arch/arm/isa/insts/mem.isa
+++ b/src/arch/arm/isa/insts/mem.isa
@@ -180,14 +180,14 @@ let {{
             memSuffix = ''
         elif size == 2:
             if sign:
-                memSuffix = '.sh'
+                memSuffix = '_sh'
             else:
-                memSuffix = '.uh'
+                memSuffix = '_uh'
         elif size == 1:
             if sign:
-                memSuffix = '.sb'
+                memSuffix = '_sb'
             else:
-                memSuffix = '.ub'
+                memSuffix = '_ub'
         else:
             raise Exception, "Unrecognized size for access %d" % size
 
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 4d8ea66a2..2cf54fcdb 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -287,7 +287,7 @@ let {{
 
     sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp",
                             { "code":
-                              "Dest = sext<8>((uint8_t)(Op1.ud >> imm));",
+                              "Dest = sext<8>((uint8_t)(Op1_ud >> imm));",
                               "predicate_test": predicateTest }, [])
     header_output += RegImmRegOpDeclare.subst(sxtbIop)
     decoder_output += RegImmRegOpConstructor.subst(sxtbIop)
@@ -296,7 +296,7 @@ let {{
     sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp",
                              { "code":
                                '''
-                                   Dest = sext<8>((uint8_t)(Op2.ud >> imm)) +
+                                   Dest = sext<8>((uint8_t)(Op2_ud >> imm)) +
                                           Op1;
                                ''',
                                "predicate_test": predicateTest }, [])
@@ -359,7 +359,7 @@ let {{
     exec_output += PredOpExecute.subst(sxtahIop)
 
     uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp",
-                            { "code": "Dest = (uint8_t)(Op1.ud >> imm);",
+                            { "code": "Dest = (uint8_t)(Op1_ud >> imm);",
                               "predicate_test": predicateTest }, [])
     header_output += RegImmRegOpDeclare.subst(uxtbIop)
     decoder_output += RegImmRegOpConstructor.subst(uxtbIop)
@@ -367,7 +367,7 @@ let {{
 
     uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp",
                              { "code":
-                               "Dest = (uint8_t)(Op2.ud >> imm) + Op1;",
+                               "Dest = (uint8_t)(Op2_ud >> imm) + Op1;",
                                "predicate_test": predicateTest }, [])
     header_output += RegRegRegImmOpDeclare.subst(uxtabIop)
     decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop)
diff --git a/src/arch/arm/isa/insts/mult.isa b/src/arch/arm/isa/insts/mult.isa
index fe4390956..7d084a671 100644
--- a/src/arch/arm/isa/insts/mult.isa
+++ b/src/arch/arm/isa/insts/mult.isa
@@ -135,29 +135,29 @@ let {{
     buildMult3Inst    ("mul", "Reg0 = resTemp = Reg1 * Reg2;")
     buildMult4InstCc  ("smlabb", '''Reg0 = resTemp =
                                         sext<16>(bits(Reg1, 15, 0)) *
-                                        sext<16>(bits(Reg2.sw, 15, 0)) +
-                                        Reg3.sw;
+                                        sext<16>(bits(Reg2_sw, 15, 0)) +
+                                        Reg3_sw;
                                  resTemp = bits(resTemp, 32) !=
                                            bits(resTemp, 31);
                                  ''', "overflow")
     buildMult4InstCc  ("smlabt", '''Reg0 = resTemp =
                                         sext<16>(bits(Reg1, 15, 0)) *
-                                        sext<16>(bits(Reg2.sw, 31, 16)) +
-                                        Reg3.sw;
+                                        sext<16>(bits(Reg2_sw, 31, 16)) +
+                                        Reg3_sw;
                                  resTemp = bits(resTemp, 32) !=
                                            bits(resTemp, 31);
                                  ''', "overflow")
     buildMult4InstCc  ("smlatb", '''Reg0 = resTemp =
                                         sext<16>(bits(Reg1, 31, 16)) *
-                                        sext<16>(bits(Reg2.sw, 15, 0)) +
-                                        Reg3.sw;
+                                        sext<16>(bits(Reg2_sw, 15, 0)) +
+                                        Reg3_sw;
                                  resTemp = bits(resTemp, 32) !=
                                            bits(resTemp, 31);
                                  ''', "overflow")
     buildMult4InstCc  ("smlatt", '''Reg0 = resTemp =
                                         sext<16>(bits(Reg1, 31, 16)) *
-                                        sext<16>(bits(Reg2.sw, 31, 16)) +
-                                        Reg3.sw;
+                                        sext<16>(bits(Reg2_sw, 31, 16)) +
+                                        Reg3_sw;
                                  resTemp = bits(resTemp, 32) !=
                                            bits(resTemp, 31);
                                  ''', "overflow")
@@ -166,7 +166,7 @@ let {{
                                         sext<16>(bits(Reg2, 31, 16)) +
                                         sext<16>(bits(Reg1, 15, 0)) *
                                         sext<16>(bits(Reg2, 15, 0)) +
-                                        Reg3.sw;
+                                        Reg3_sw;
                                     resTemp = bits(resTemp, 32) !=
                                               bits(resTemp, 31);
                                 ''', "overflow")
@@ -175,74 +175,74 @@ let {{
                                          sext<16>(bits(Reg2, 15, 0)) +
                                          sext<16>(bits(Reg1, 15, 0)) *
                                          sext<16>(bits(Reg2, 31, 16)) +
-                                         Reg3.sw;
+                                         Reg3_sw;
                                     resTemp = bits(resTemp, 32) !=
                                               bits(resTemp, 31);
                                  ''', "overflow")
     buildMult4Inst    ("smlal", '''resTemp = sext<32>(Reg2) * sext<32>(Reg3) +
-                                       (int64_t)((Reg1.ud << 32) | Reg0.ud);
-                                   Reg0.ud = (uint32_t)resTemp;
-                                   Reg1.ud = (uint32_t)(resTemp >> 32);
+                                       (int64_t)((Reg1_ud << 32) | Reg0_ud);
+                                   Reg0_ud = (uint32_t)resTemp;
+                                   Reg1_ud = (uint32_t)(resTemp >> 32);
                                 ''', "llbit")
     buildMult4InstUnCc("smlalbb", '''resTemp = sext<16>(bits(Reg2, 15, 0)) *
                                                sext<16>(bits(Reg3, 15, 0)) +
-                                               (int64_t)((Reg1.ud << 32) |
-                                                         Reg0.ud);
-                                     Reg0.ud = (uint32_t)resTemp;
-                                     Reg1.ud = (uint32_t)(resTemp >> 32);
+                                               (int64_t)((Reg1_ud << 32) |
+                                                         Reg0_ud);
+                                     Reg0_ud = (uint32_t)resTemp;
+                                     Reg1_ud = (uint32_t)(resTemp >> 32);
                                   ''')
     buildMult4InstUnCc("smlalbt", '''resTemp = sext<16>(bits(Reg2, 15, 0)) *
                                                sext<16>(bits(Reg3, 31, 16)) +
-                                               (int64_t)((Reg1.ud << 32) |
-                                                         Reg0.ud);
-                                     Reg0.ud = (uint32_t)resTemp;
-                                     Reg1.ud = (uint32_t)(resTemp >> 32);
+                                               (int64_t)((Reg1_ud << 32) |
+                                                         Reg0_ud);
+                                     Reg0_ud = (uint32_t)resTemp;
+                                     Reg1_ud = (uint32_t)(resTemp >> 32);
                                   ''')
     buildMult4InstUnCc("smlaltb", '''resTemp = sext<16>(bits(Reg2, 31, 16)) *
                                                sext<16>(bits(Reg3, 15, 0)) +
-                                               (int64_t)((Reg1.ud << 32) |
-                                                         Reg0.ud);
-                                     Reg0.ud = (uint32_t)resTemp;
-                                     Reg1.ud = (uint32_t)(resTemp >> 32);
+                                               (int64_t)((Reg1_ud << 32) |
+                                                         Reg0_ud);
+                                     Reg0_ud = (uint32_t)resTemp;
+                                     Reg1_ud = (uint32_t)(resTemp >> 32);
                                   ''')
     buildMult4InstUnCc("smlaltt", '''resTemp = sext<16>(bits(Reg2, 31, 16)) *
                                                sext<16>(bits(Reg3, 31, 16)) +
-                                               (int64_t)((Reg1.ud << 32) |
-                                                         Reg0.ud);
-                                     Reg0.ud = (uint32_t)resTemp;
-                                     Reg1.ud = (uint32_t)(resTemp >> 32);
+                                               (int64_t)((Reg1_ud << 32) |
+                                                         Reg0_ud);
+                                     Reg0_ud = (uint32_t)resTemp;
+                                     Reg1_ud = (uint32_t)(resTemp >> 32);
                                   ''')
     buildMult4InstUnCc("smlald", '''resTemp =
                                         sext<16>(bits(Reg2, 31, 16)) *
                                         sext<16>(bits(Reg3, 31, 16)) +
                                         sext<16>(bits(Reg2, 15, 0)) *
                                         sext<16>(bits(Reg3, 15, 0)) +
-                                        (int64_t)((Reg1.ud << 32) |
-                                                  Reg0.ud);
-                                    Reg0.ud = (uint32_t)resTemp;
-                                    Reg1.ud = (uint32_t)(resTemp >> 32);
+                                        (int64_t)((Reg1_ud << 32) |
+                                                  Reg0_ud);
+                                    Reg0_ud = (uint32_t)resTemp;
+                                    Reg1_ud = (uint32_t)(resTemp >> 32);
                                  ''')
     buildMult4InstUnCc("smlaldx", '''resTemp =
                                          sext<16>(bits(Reg2, 31, 16)) *
                                          sext<16>(bits(Reg3, 15, 0)) +
                                          sext<16>(bits(Reg2, 15, 0)) *
                                          sext<16>(bits(Reg3, 31, 16)) +
-                                         (int64_t)((Reg1.ud << 32) |
-                                                   Reg0.ud);
-                                     Reg0.ud = (uint32_t)resTemp;
-                                     Reg1.ud = (uint32_t)(resTemp >> 32);
+                                         (int64_t)((Reg1_ud << 32) |
+                                                   Reg0_ud);
+                                     Reg0_ud = (uint32_t)resTemp;
+                                     Reg1_ud = (uint32_t)(resTemp >> 32);
                                   ''')
     buildMult4InstCc  ("smlawb", '''Reg0 = resTemp =
-                                        (Reg1.sw *
+                                        (Reg1_sw *
                                          sext<16>(bits(Reg2, 15, 0)) +
-                                         ((int64_t)Reg3.sw << 16)) >> 16;
+                                         ((int64_t)Reg3_sw << 16)) >> 16;
                                     resTemp = bits(resTemp, 32) !=
                                               bits(resTemp, 31);
                                  ''', "overflow")
     buildMult4InstCc  ("smlawt", '''Reg0 = resTemp =
-                                        (Reg1.sw *
+                                        (Reg1_sw *
                                          sext<16>(bits(Reg2, 31, 16)) +
-                                         ((int64_t)Reg3.sw << 16)) >> 16;
+                                         ((int64_t)Reg3_sw << 16)) >> 16;
                                     resTemp = bits(resTemp, 32) !=
                                               bits(resTemp, 31);
                                  ''', "overflow")
@@ -251,7 +251,7 @@ let {{
                                        sext<16>(bits(Reg2, 15, 0)) -
                                        sext<16>(bits(Reg1, 31, 16)) *
                                        sext<16>(bits(Reg2, 31, 16)) +
-                                       Reg3.sw;
+                                       Reg3_sw;
                                     resTemp = bits(resTemp, 32) !=
                                               bits(resTemp, 31);
                                 ''', "overflow")
@@ -260,7 +260,7 @@ let {{
                                         sext<16>(bits(Reg2, 31, 16)) -
                                         sext<16>(bits(Reg1, 31, 16)) *
                                         sext<16>(bits(Reg2, 15, 0)) +
-                                        Reg3.sw;
+                                        Reg3_sw;
                                     resTemp = bits(resTemp, 32) !=
                                               bits(resTemp, 31);
                                  ''', "overflow")
@@ -269,50 +269,50 @@ let {{
                                         sext<16>(bits(Reg3, 15, 0)) -
                                         sext<16>(bits(Reg2, 31, 16)) *
                                         sext<16>(bits(Reg3, 31, 16)) +
-                                        (int64_t)((Reg1.ud << 32) |
-                                                  Reg0.ud);
-                                    Reg0.ud = (uint32_t)resTemp;
-                                    Reg1.ud = (uint32_t)(resTemp >> 32);
+                                        (int64_t)((Reg1_ud << 32) |
+                                                  Reg0_ud);
+                                    Reg0_ud = (uint32_t)resTemp;
+                                    Reg1_ud = (uint32_t)(resTemp >> 32);
                                  ''')
     buildMult4InstUnCc("smlsldx", '''resTemp =
                                          sext<16>(bits(Reg2, 15, 0)) *
                                          sext<16>(bits(Reg3, 31, 16)) -
                                          sext<16>(bits(Reg2, 31, 16)) *
                                          sext<16>(bits(Reg3, 15, 0)) +
-                                         (int64_t)((Reg1.ud << 32) |
-                                                   Reg0.ud);
-                                     Reg0.ud = (uint32_t)resTemp;
-                                     Reg1.ud = (uint32_t)(resTemp >> 32);
+                                         (int64_t)((Reg1_ud << 32) |
+                                                   Reg0_ud);
+                                     Reg0_ud = (uint32_t)resTemp;
+                                     Reg1_ud = (uint32_t)(resTemp >> 32);
                                   ''')
     buildMult4InstUnCc("smmla", '''Reg0 = resTemp =
-                                       ((int64_t)(Reg3.ud << 32) +
-                                        (int64_t)Reg1.sw *
-                                        (int64_t)Reg2.sw) >> 32;
+                                       ((int64_t)(Reg3_ud << 32) +
+                                        (int64_t)Reg1_sw *
+                                        (int64_t)Reg2_sw) >> 32;
                                 ''')
     buildMult4InstUnCc("smmlar", '''Reg0 = resTemp =
-                                        ((int64_t)(Reg3.ud << 32) +
-                                         (int64_t)Reg1.sw *
-                                         (int64_t)Reg2.sw +
+                                        ((int64_t)(Reg3_ud << 32) +
+                                         (int64_t)Reg1_sw *
+                                         (int64_t)Reg2_sw +
                                          ULL(0x80000000)) >> 32;
                                  ''')
     buildMult4InstUnCc("smmls", '''Reg0 = resTemp =
-                                       ((int64_t)(Reg3.ud << 32) -
-                                        (int64_t)Reg1.sw *
-                                        (int64_t)Reg2.sw) >> 32;
+                                       ((int64_t)(Reg3_ud << 32) -
+                                        (int64_t)Reg1_sw *
+                                        (int64_t)Reg2_sw) >> 32;
                                 ''')
     buildMult4InstUnCc("smmlsr", '''Reg0 = resTemp =
-                                        ((int64_t)(Reg3.ud << 32) -
-                                         (int64_t)Reg1.sw *
-                                         (int64_t)Reg2.sw +
+                                        ((int64_t)(Reg3_ud << 32) -
+                                         (int64_t)Reg1_sw *
+                                         (int64_t)Reg2_sw +
                                          ULL(0x80000000)) >> 32;
                                  ''')
     buildMult3InstUnCc("smmul", '''Reg0 = resTemp =
-                                       ((int64_t)Reg1.sw *
-                                        (int64_t)Reg2.sw) >> 32;
+                                       ((int64_t)Reg1_sw *
+                                        (int64_t)Reg2_sw) >> 32;
                                 ''')
     buildMult3InstUnCc("smmulr", '''Reg0 = resTemp =
-                                        ((int64_t)Reg1.sw *
-                                         (int64_t)Reg2.sw +
+                                        ((int64_t)Reg1_sw *
+                                         (int64_t)Reg2_sw +
                                          ULL(0x80000000)) >> 32;
                                  ''')
     buildMult3InstCc  ("smuad", '''Reg0 = resTemp =
@@ -347,17 +347,17 @@ let {{
                                          sext<16>(bits(Reg1, 31, 16)) *
                                          sext<16>(bits(Reg2, 31, 16));
                                  ''')
-    buildMult4Inst    ("smull", '''resTemp = (int64_t)Reg2.sw *
-                                             (int64_t)Reg3.sw;
+    buildMult4Inst    ("smull", '''resTemp = (int64_t)Reg2_sw *
+                                             (int64_t)Reg3_sw;
                                    Reg1 = (int32_t)(resTemp >> 32);
                                    Reg0 = (int32_t)resTemp;
                                 ''', "llbit")
     buildMult3InstUnCc("smulwb", '''Reg0 = resTemp =
-                                        (Reg1.sw *
+                                        (Reg1_sw *
                                          sext<16>(bits(Reg2, 15, 0))) >> 16;
                                  ''')
     buildMult3InstUnCc("smulwt", '''Reg0 = resTemp =
-                                        (Reg1.sw *
+                                        (Reg1_sw *
                                          sext<16>(bits(Reg2, 31, 16))) >> 16;
                                  ''')
     buildMult3InstUnCc("smusd", '''Reg0 = resTemp =
@@ -372,17 +372,17 @@ let {{
                                         sext<16>(bits(Reg1, 31, 16)) *
                                         sext<16>(bits(Reg2, 15, 0));
                                  ''')
-    buildMult4InstUnCc("umaal", '''resTemp = Reg2.ud * Reg3.ud +
-                                             Reg0.ud + Reg1.ud;
-                                   Reg1.ud = (uint32_t)(resTemp >> 32);
-                                   Reg0.ud = (uint32_t)resTemp;
+    buildMult4InstUnCc("umaal", '''resTemp = Reg2_ud * Reg3_ud +
+                                             Reg0_ud + Reg1_ud;
+                                   Reg1_ud = (uint32_t)(resTemp >> 32);
+                                   Reg0_ud = (uint32_t)resTemp;
                                 ''')
-    buildMult4Inst    ("umlal", '''resTemp = Reg2.ud * Reg3.ud + Reg0.ud +
-                                             (Reg1.ud << 32);
-                                   Reg1.ud = (uint32_t)(resTemp >> 32);
-                                   Reg0.ud = (uint32_t)resTemp;
+    buildMult4Inst    ("umlal", '''resTemp = Reg2_ud * Reg3_ud + Reg0_ud +
+                                             (Reg1_ud << 32);
+                                   Reg1_ud = (uint32_t)(resTemp >> 32);
+                                   Reg0_ud = (uint32_t)resTemp;
                                 ''', "llbit")
-    buildMult4Inst    ("umull", '''resTemp = Reg2.ud * Reg3.ud;
+    buildMult4Inst    ("umull", '''resTemp = Reg2_ud * Reg3_ud;
                                    Reg1 = (uint32_t)(resTemp >> 32);
                                    Reg0 = (uint32_t)resTemp;
                                 ''', "llbit")
diff --git a/src/arch/arm/isa/insts/neon.isa b/src/arch/arm/isa/insts/neon.isa
index 083d1ebaf..fdb6237c0 100644
--- a/src/arch/arm/isa/insts/neon.isa
+++ b/src/arch/arm/isa/insts/neon.isa
@@ -639,12 +639,12 @@ let {{
         '''
         for reg in range(rCount):
             eWalkCode += '''
-                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
-                srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d.uw);
+                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
+                srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d_uw);
             ''' % { "reg" : reg }
             if readDest:
                 eWalkCode += '''
-                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);
+                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
                 ''' % { "reg" : reg }
         readDestCode = ''
         if readDest:
@@ -677,7 +677,7 @@ let {{
             ''' % { "op" : op, "readDest" : readDestCode }
         for reg in range(rCount):
             eWalkCode += '''
-            FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);
+            FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
             ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "RegRegRegOp",
@@ -758,7 +758,7 @@ let {{
         for reg in range(rCount):
             if toInt:
                 eWalkCode += '''
-                FpDestP%(reg)d.uw = destRegs.regs[%(reg)d];
+                FpDestP%(reg)d_uw = destRegs.regs[%(reg)d];
                 ''' % { "reg" : reg }
             else:
                 eWalkCode += '''
@@ -798,16 +798,16 @@ let {{
         ''' % (src1Prefix, src2Prefix, destPrefix)
         for reg in range(src1Cnt):
             eWalkCode += '''
-                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
+                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
             ''' % { "reg" : reg }
         for reg in range(src2Cnt):
             eWalkCode += '''
-                srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d.uw);
+                srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d_uw);
             ''' % { "reg" : reg }
         if readDest:
             for reg in range(destCnt):
                 eWalkCode += '''
-                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);
+                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
                 ''' % { "reg" : reg }
         readDestCode = ''
         if readDest:
@@ -826,7 +826,7 @@ let {{
                 "destPrefix" : destPrefix }
         for reg in range(destCnt):
             eWalkCode += '''
-            FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);
+            FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
             ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "RegRegRegOp",
@@ -860,12 +860,12 @@ let {{
         '''
         for reg in range(rCount):
             eWalkCode += '''
-                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
-                srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d.uw);
+                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
+                srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d_uw);
             ''' % { "reg" : reg }
             if readDest:
                 eWalkCode += '''
-                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);
+                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
                 ''' % { "reg" : reg }
         readDestCode = ''
         if readDest:
@@ -890,7 +890,7 @@ let {{
         ''' % { "op" : op, "readDest" : readDestCode }
         for reg in range(rCount):
             eWalkCode += '''
-            FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);
+            FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
             ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "RegRegRegImmOp",
@@ -914,13 +914,13 @@ let {{
         '''
         for reg in range(rCount):
             eWalkCode += '''
-                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
-                srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d.uw);;
+                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
+                srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d_uw);;
             ''' % { "reg" : reg }
         if readDest:
             for reg in range(2 * rCount):
                 eWalkCode += '''
-                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);
+                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
                 ''' % { "reg" : reg }
         readDestCode = ''
         if readDest:
@@ -945,7 +945,7 @@ let {{
         ''' % { "op" : op, "readDest" : readDestCode }
         for reg in range(2 * rCount):
             eWalkCode += '''
-            FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);
+            FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
             ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "RegRegRegImmOp",
@@ -1021,11 +1021,11 @@ let {{
         '''
         for reg in range(rCount):
             eWalkCode += '''
-                srcRegs1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
+                srcRegs1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
             ''' % { "reg" : reg }
             if readDest:
                 eWalkCode += '''
-                    destRegs.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);
+                    destRegs.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
                 ''' % { "reg" : reg }
         readDestCode = ''
         if readDest:
@@ -1055,7 +1055,7 @@ let {{
                 "writeDest" : writeDestCode }
         for reg in range(rCount):
             eWalkCode += '''
-            FpDestP%(reg)d.uw = gtoh(destRegs.regs[%(reg)d]);
+            FpDestP%(reg)d_uw = gtoh(destRegs.regs[%(reg)d]);
             ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "RegRegImmOp",
@@ -1078,12 +1078,12 @@ let {{
         '''
         for reg in range(4):
             eWalkCode += '''
-                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
+                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
             ''' % { "reg" : reg }
         if readDest:
             for reg in range(2):
                 eWalkCode += '''
-                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);
+                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
                 ''' % { "reg" : reg }
         readDestCode = ''
         if readDest:
@@ -1099,7 +1099,7 @@ let {{
         ''' % { "op" : op, "readDest" : readDestCode }
         for reg in range(2):
             eWalkCode += '''
-            FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);
+            FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
             ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "RegRegImmOp",
@@ -1122,12 +1122,12 @@ let {{
         '''
         for reg in range(2):
             eWalkCode += '''
-                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
+                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
             ''' % { "reg" : reg }
         if readDest:
             for reg in range(4):
                 eWalkCode += '''
-                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);
+                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
                 ''' % { "reg" : reg }
         readDestCode = ''
         if readDest:
@@ -1143,7 +1143,7 @@ let {{
         ''' % { "op" : op, "readDest" : readDestCode }
         for reg in range(4):
             eWalkCode += '''
-            FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);
+            FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
             ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "RegRegImmOp",
@@ -1165,11 +1165,11 @@ let {{
         '''
         for reg in range(rCount):
             eWalkCode += '''
-                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
+                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
             ''' % { "reg" : reg }
             if readDest:
                 eWalkCode += '''
-                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);
+                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
                 ''' % { "reg" : reg }
         readDestCode = ''
         if readDest:
@@ -1186,7 +1186,7 @@ let {{
         ''' % { "op" : op, "readDest" : readDestCode }
         for reg in range(rCount):
             eWalkCode += '''
-            FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);
+            FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
             ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "RegRegOp",
@@ -1208,11 +1208,11 @@ let {{
         '''
         for reg in range(rCount):
             eWalkCode += '''
-                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
+                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
             ''' % { "reg" : reg }
             if readDest:
                 eWalkCode += '''
-                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);
+                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
                 ''' % { "reg" : reg }
         readDestCode = ''
         if readDest:
@@ -1228,7 +1228,7 @@ let {{
         ''' % { "op" : op, "readDest" : readDestCode }
         for reg in range(rCount):
             eWalkCode += '''
-            FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);
+            FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
             ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "RegRegImmOp",
@@ -1250,8 +1250,8 @@ let {{
         '''
         for reg in range(rCount):
             eWalkCode += '''
-                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
-                destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);
+                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
+                destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
             ''' % { "reg" : reg }
             if readDest:
                 eWalkCode += '''
@@ -1262,8 +1262,8 @@ let {{
         eWalkCode += op
         for reg in range(rCount):
             eWalkCode += '''
-            FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);
-            FpOp1P%(reg)d.uw = gtoh(srcReg1.regs[%(reg)d]);
+            FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
+            FpOp1P%(reg)d_uw = gtoh(srcReg1.regs[%(reg)d]);
             ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "RegRegOp",
@@ -1325,7 +1325,7 @@ let {{
         for reg in range(rCount):
             if toInt:
                 eWalkCode += '''
-                FpDestP%(reg)d.uw = destRegs.regs[%(reg)d];
+                FpDestP%(reg)d_uw = destRegs.regs[%(reg)d];
                 ''' % { "reg" : reg }
             else:
                 eWalkCode += '''
@@ -1352,11 +1352,11 @@ let {{
         '''
         for reg in range(rCount):
             eWalkCode += '''
-                srcRegs.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
+                srcRegs.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
             ''' % { "reg" : reg }
             if readDest:
                 eWalkCode += '''
-                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);
+                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
                 ''' % { "reg" : reg }
         readDestCode = ''
         if readDest:
@@ -1373,7 +1373,7 @@ let {{
         ''' % { "op" : op, "readDest" : readDestCode }
         for reg in range(rCount):
             eWalkCode += '''
-            FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);
+            FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
             ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "RegRegOp",
@@ -1396,12 +1396,12 @@ let {{
         '''
         for reg in range(4):
             eWalkCode += '''
-                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
+                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
             ''' % { "reg" : reg }
         if readDest:
             for reg in range(2):
                 eWalkCode += '''
-                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);
+                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
                 ''' % { "reg" : reg }
         readDestCode = ''
         if readDest:
@@ -1417,7 +1417,7 @@ let {{
         ''' % { "op" : op, "readDest" : readDestCode }
         for reg in range(2):
             eWalkCode += '''
-            FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);
+            FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
             ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "RegRegOp",
@@ -1440,7 +1440,7 @@ let {{
         if readDest:
             for reg in range(rCount):
                 eWalkCode += '''
-                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);
+                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
                 ''' % { "reg" : reg }
         readDestCode = ''
         if readDest:
@@ -1455,7 +1455,7 @@ let {{
         ''' % { "op" : op, "readDest" : readDestCode }
         for reg in range(rCount):
             eWalkCode += '''
-            FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);
+            FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
             ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "RegImmOp",
@@ -1478,12 +1478,12 @@ let {{
         '''
         for reg in range(2):
             eWalkCode += '''
-                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
+                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
             ''' % { "reg" : reg }
         if readDest:
             for reg in range(4):
                 eWalkCode += '''
-                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw);
+                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
                 ''' % { "reg" : reg }
         readDestCode = ''
         if readDest:
@@ -1499,7 +1499,7 @@ let {{
         ''' % { "op" : op, "readDest" : readDestCode }
         for reg in range(4):
             eWalkCode += '''
-            FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);
+            FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
             ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "RegRegOp",
@@ -3190,7 +3190,7 @@ let {{
         '''
         for reg in range(rCount):
             eWalkCode += '''
-            FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);
+            FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
             ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "RegRegOp",
@@ -3270,13 +3270,13 @@ let {{
         '''
         for reg in range(rCount):
             eWalkCode += simdEnabledCheckCode + '''
-                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);
-                srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d.uw);
+                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
+                srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d_uw);
             ''' % { "reg" : reg }
         eWalkCode += op
         for reg in range(rCount):
             eWalkCode += '''
-            FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]);
+            FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
             ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "RegRegRegImmOp",
@@ -3330,15 +3330,15 @@ let {{
             const unsigned length = %(length)d;
             const bool isVtbl = %(isVtbl)s;
 
-            srcReg2.regs[0] = htog(FpOp2P0.uw);
-            srcReg2.regs[1] = htog(FpOp2P1.uw);
+            srcReg2.regs[0] = htog(FpOp2P0_uw);
+            srcReg2.regs[1] = htog(FpOp2P1_uw);
 
-            destReg.regs[0] = htog(FpDestP0.uw);
-            destReg.regs[1] = htog(FpDestP1.uw);
+            destReg.regs[0] = htog(FpDestP0_uw);
+            destReg.regs[1] = htog(FpDestP1_uw);
         ''' % { "length" : length, "isVtbl" : isVtbl }
         for reg in range(8):
             if reg < length * 2:
-                code += 'table.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);\n' % \
+                code += 'table.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);\n' % \
                         { "reg" : reg }
             else:
                 code += 'table.regs[%(reg)d] = 0;\n' % { "reg" : reg }
@@ -3354,8 +3354,8 @@ let {{
             }
         }
 
-        FpDestP0.uw = gtoh(destReg.regs[0]);
-        FpDestP1.uw = gtoh(destReg.regs[1]);
+        FpDestP0_uw = gtoh(destReg.regs[0]);
+        FpDestP1_uw = gtoh(destReg.regs[1]);
         '''
         iop = InstObjParams(name, Name,
                             "RegRegRegOp",
diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa
index c01478cfa..80846053b 100644
--- a/src/arch/arm/isa/insts/str.isa
+++ b/src/arch/arm/isa/insts/str.isa
@@ -110,8 +110,8 @@ let {{
                 wbDiff = 8
             accCode = '''
             CPSR cpsr = Cpsr;
-            Mem.ud = (uint64_t)cSwap(LR.uw, cpsr.e) |
-                     ((uint64_t)cSwap(Spsr.uw, cpsr.e) << 32);
+            Mem_ud = (uint64_t)cSwap(LR_uw, cpsr.e) |
+                     ((uint64_t)cSwap(Spsr_uw, cpsr.e) << 32);
             '''
 
             global header_output, decoder_output, exec_output
@@ -198,7 +198,7 @@ let {{
 
             # Code that actually handles the access
             if self.flavor == "fp":
-                accCode = 'Mem%(suffix)s = cSwap(FpDest.uw, ((CPSR)Cpsr).e);'
+                accCode = 'Mem%(suffix)s = cSwap(FpDest_uw, ((CPSR)Cpsr).e);'
             else:
                 accCode = \
                     'Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);'
@@ -273,15 +273,15 @@ let {{
             # Code that actually handles the access
             if self.flavor == "fp":
                 accCode = '''
-                uint64_t swappedMem  = (uint64_t)FpDest.uw |
-                                       ((uint64_t)FpDest2.uw << 32);
-                Mem.ud = cSwap(swappedMem, ((CPSR)Cpsr).e);
+                uint64_t swappedMem  = (uint64_t)FpDest_uw |
+                                       ((uint64_t)FpDest2_uw << 32);
+                Mem_ud = cSwap(swappedMem, ((CPSR)Cpsr).e);
                 '''
             else:
                 accCode = '''
                 CPSR cpsr = Cpsr;
-                Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) |
-                         ((uint64_t)cSwap(Dest2.uw, cpsr.e) << 32);
+                Mem_ud = (uint64_t)cSwap(Dest_uw, cpsr.e) |
+                         ((uint64_t)cSwap(Dest2_uw, cpsr.e) << 32);
                 '''
 
             self.codeBlobs["memacc_code"] = accCode
diff --git a/src/arch/arm/isa/insts/swap.isa b/src/arch/arm/isa/insts/swap.isa
index 3be4278fa..f319e75aa 100644
--- a/src/arch/arm/isa/insts/swap.isa
+++ b/src/arch/arm/isa/insts/swap.isa
@@ -82,7 +82,7 @@ let {{
     '''
 
     SwapInst('swp', 'Swp', 'EA = Base;',
-             swpPreAccCode + 'Mem = cSwap(Op1.uw, ((CPSR)Cpsr).e);',
+             swpPreAccCode + 'Mem = cSwap(Op1_uw, ((CPSR)Cpsr).e);',
              'Dest = cSwap((uint32_t)memData, ((CPSR)Cpsr).e);',
              ['Request::MEM_SWAP',
               'ArmISA::TLB::AlignWord',
@@ -90,8 +90,8 @@ let {{
               ['IsStoreConditional']).emit()
 
     SwapInst('swpb', 'Swpb', 'EA = Base;',
-             swpPreAccCode + 'Mem.ub = cSwap(Op1.ub, ((CPSR)Cpsr).e);',
-             'Dest.ub = cSwap((uint8_t)memData, ((CPSR)Cpsr).e);',
+             swpPreAccCode + 'Mem_ub = cSwap(Op1_ub, ((CPSR)Cpsr).e);',
+             'Dest_ub = cSwap((uint8_t)memData, ((CPSR)Cpsr).e);',
              ['Request::MEM_SWAP',
               'ArmISA::TLB::AlignByte',
               'ArmISA::TLB::MustBeOne'],
-- 
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