From 9d3b9e96c56386ee6539657c21cba95e118e576a Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 15 Oct 2019 21:48:31 -0700 Subject: cpu,arm: Push the stage 2 MMUs out of the CPU into the TLBs. This regularizes the TLB setup in the CPU so that ARM is no longer a special case with extra objects. Change-Id: I739b82578ff74f8f9777cd7e34cd5227b47b186c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21842 Tested-by: kokoro Reviewed-by: Jason Lowe-Power Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg --- src/arch/arm/ArmTLB.py | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'src/arch/arm') diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py index 4a6b3e7cd..d2334630e 100644 --- a/src/arch/arm/ArmTLB.py +++ b/src/arch/arm/ArmTLB.py @@ -90,11 +90,17 @@ class ArmStage2MMU(SimObject): class ArmStage2IMMU(ArmStage2MMU): # We rely on the itb being a parameter of the CPU, and get the # appropriate object that way - tlb = Parent.itb + tlb = Parent.any stage2_tlb = ArmStage2TLB() class ArmStage2DMMU(ArmStage2MMU): # We rely on the dtb being a parameter of the CPU, and get the # appropriate object that way - tlb = Parent.dtb + tlb = Parent.any stage2_tlb = ArmStage2TLB() + +class ArmITB(ArmTLB): + stage2_mmu = ArmStage2IMMU() + +class ArmDTB(ArmTLB): + stage2_mmu = ArmStage2DMMU() -- cgit v1.2.3