From aafa5c3f86ea54f5e6e88009be656aeec12eef5f Mon Sep 17 00:00:00 2001
From: Nilay Vaish <nilay@cs.wisc.edu>
Date: Tue, 28 Jul 2015 01:58:04 -0500
Subject: revert 5af8f40d8f2c

---
 src/arch/arm/insts/static_inst.cc |  2 --
 src/arch/arm/isa.hh               |  7 -------
 src/arch/arm/registers.hh         | 10 +---------
 src/arch/arm/utility.cc           |  3 ---
 4 files changed, 1 insertion(+), 21 deletions(-)

(limited to 'src/arch/arm')

diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc
index 417496579..9f878ac4d 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -337,8 +337,6 @@ ArmStaticInst::printReg(std::ostream &os, int reg) const
       case CCRegClass:
         ccprintf(os, "cc_%s", ArmISA::ccRegName[rel_reg]);
         break;
-      case VectorRegClass:
-        panic("ARM ISA does not have any vector registers yet!");
     }
 }
 
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 1e7edd637..a07017c17 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -287,13 +287,6 @@ namespace ArmISA
             return reg;
         }
 
-        int
-        flattenVectorIndex(int reg) const
-        {
-            assert(reg >= 0);
-            return reg;
-        }
-
         int
         flattenMiscIndex(int reg) const
         {
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index e57802e53..23fc20450 100644
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -72,12 +72,6 @@ typedef uint64_t MiscReg;
 // condition code register; must be at least 32 bits for FpCondCodes
 typedef uint64_t CCReg;
 
-// vector register file entry type
-typedef uint64_t VectorRegElement;
-const int NumVectorRegElements = 0;
-const int VectorRegBytes = NumVectorRegElements * sizeof(VectorRegElement);
-typedef std::array<VectorRegElement, NumVectorRegElements> VectorReg;
-
 // Constants Related to the number of registers
 const int NumIntArchRegs = NUM_ARCH_INTREGS;
 // The number of single precision floating point registers
@@ -88,7 +82,6 @@ const int NumFloatSpecialRegs = 32;
 const int NumIntRegs = NUM_INTREGS;
 const int NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs;
 const int NumCCRegs = NUM_CCREGS;
-const int NumVectorRegs = 0;
 const int NumMiscRegs = NUM_MISCREGS;
 
 #define ISA_HAS_CC_REGS
@@ -119,8 +112,7 @@ const int SyscallSuccessReg = ReturnValueReg;
 // These help enumerate all the registers for dependence tracking.
 const int FP_Reg_Base = NumIntRegs * (MODE_MAXMODE + 1);
 const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs;
-const int Vector_Reg_Base = CC_Reg_Base + NumCCRegs;
-const int Misc_Reg_Base = Vector_Reg_Base + NumVectorRegs;
+const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs;
 const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
 
 typedef union {
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index e1f9dfe04..34fcfd482 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -156,9 +156,6 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
     for (int i = 0; i < NumCCRegs; i++)
         dest->setCCReg(i, src->readCCReg(i));
 
-    // Copy vector registers when vector registers put to use.
-    assert(NumVectorRegs == 0);
-
     for (int i = 0; i < NumMiscRegs; i++)
         dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
 
-- 
cgit v1.2.3