From c3bf29bbeabdd3510a2e3c81c653c2931ad26e64 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 2 Jun 2010 12:58:11 -0500
Subject: ARM: Implement the udiv instruction.

---
 src/arch/arm/isa/formats/mult.isa |  2 +-
 src/arch/arm/isa/insts/div.isa    | 14 ++++++++++++++
 2 files changed, 15 insertions(+), 1 deletion(-)

(limited to 'src/arch/arm')

diff --git a/src/arch/arm/isa/formats/mult.isa b/src/arch/arm/isa/formats/mult.isa
index 8b3720e49..cfd00b1a5 100644
--- a/src/arch/arm/isa/formats/mult.isa
+++ b/src/arch/arm/isa/formats/mult.isa
@@ -303,7 +303,7 @@ def format Thumb32LongMulMulAccAndDiv() {{
             break;
           case 0x3:
             if (op2 == 0xf) {
-                return new WarnUnimplemented("udiv", machInst);
+                return new Udiv(machInst, rdhi, rn, rm);
             }
             break;
           case 0x4:
diff --git a/src/arch/arm/isa/insts/div.isa b/src/arch/arm/isa/insts/div.isa
index b3bd19cdb..b240e2967 100644
--- a/src/arch/arm/isa/insts/div.isa
+++ b/src/arch/arm/isa/insts/div.isa
@@ -53,4 +53,18 @@ let {{
     header_output = RegRegRegOpDeclare.subst(sdivIop)
     decoder_output = RegRegRegOpConstructor.subst(sdivIop)
     exec_output = PredOpExecute.subst(sdivIop)
+
+    udivCode = '''
+    if (Op2.uw == 0) {
+        Dest.uw = 0;
+    } else {
+        Dest.uw = Op1.uw / Op2.uw;
+    }
+    '''
+    udivIop = InstObjParams("udiv", "Udiv", "RegRegRegOp",
+                            { "code": udivCode,
+                              "predicate_test": predicateTest }, [])
+    header_output += RegRegRegOpDeclare.subst(udivIop)
+    decoder_output += RegRegRegOpConstructor.subst(udivIop)
+    exec_output += PredOpExecute.subst(udivIop)
 }};
-- 
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