From 80a6907927461241883a47b552272702978216f8 Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Mon, 9 Jan 2012 18:08:20 -0600
Subject: ARM: Add support for initparam m5 op

---
 src/arch/arm/isa/insts/m5ops.isa | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

(limited to 'src/arch/arm')

diff --git a/src/arch/arm/isa/insts/m5ops.isa b/src/arch/arm/isa/insts/m5ops.isa
index 3b837cba9..f20908d4f 100644
--- a/src/arch/arm/isa/insts/m5ops.isa
+++ b/src/arch/arm/isa/insts/m5ops.isa
@@ -191,16 +191,18 @@ let {{
 
     initparamCode = '''
 #if FULL_SYSTEM
-    Rt = PseudoInst::initParam(xc->tcBase());
+    uint64_t ip_val  = PseudoInst::initParam(xc->tcBase());
+    R0 = bits(ip_val, 31, 0);
+    R1 = bits(ip_val, 63, 32);
 #else
     PseudoInst::panicFsOnlyPseudoInst("initparam");
-    Rt = 0;
 #endif
     '''
 
     initparamIop = InstObjParams("initparam", "Initparam", "PredOp",
                            { "code": initparamCode,
-                             "predicate_test": predicateTest })
+                             "predicate_test": predicateTest },
+                             ["IsNonSpeculative"])
     header_output += BasicDeclare.subst(initparamIop)
     decoder_output += BasicConstructor.subst(initparamIop)
     exec_output += PredOpExecute.subst(initparamIop)
-- 
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