From e17c375ddd32fbbef55a96c446a4b98b20df2ad5 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 4 Jan 2013 19:00:45 -0600 Subject: Decoder: Remove the thread context get/set from the decoder. This interface is no longer used, and getting rid of it simplifies the decoders and code that sets up the decoders. The thread context had been used to read architectural state which was used to contextualize the instruction memory as it came in. That was changed so that the state is now sent to the decoders to keep locally if/when it changes. That's significantly more efficient. Committed by: Nilay Vaish --- src/arch/arm/decoder.cc | 1 - src/arch/arm/decoder.hh | 17 +---------------- src/arch/arm/isa.cc | 2 +- 3 files changed, 2 insertions(+), 18 deletions(-) (limited to 'src/arch/arm') diff --git a/src/arch/arm/decoder.cc b/src/arch/arm/decoder.cc index b5a73d68b..e957ce0e7 100644 --- a/src/arch/arm/decoder.cc +++ b/src/arch/arm/decoder.cc @@ -32,7 +32,6 @@ #include "arch/arm/isa_traits.hh" #include "arch/arm/utility.hh" #include "base/trace.hh" -#include "cpu/thread_context.hh" #include "debug/Decoder.hh" namespace ArmISA diff --git a/src/arch/arm/decoder.hh b/src/arch/arm/decoder.hh index 9099e3e2e..83a16da4c 100644 --- a/src/arch/arm/decoder.hh +++ b/src/arch/arm/decoder.hh @@ -39,15 +39,12 @@ #include "base/types.hh" #include "cpu/static_inst.hh" -class ThreadContext; - namespace ArmISA { class Decoder { protected: - ThreadContext * tc; //The extended machine instruction being generated ExtMachInst emi; MachInst data; @@ -72,23 +69,11 @@ class Decoder foundIt = false; } - Decoder(ThreadContext * _tc) : tc(_tc), data(0), - fpscrLen(0), fpscrStride(0) + Decoder() : data(0), fpscrLen(0), fpscrStride(0) { reset(); } - ThreadContext * getTC() - { - return tc; - } - - void - setTC(ThreadContext * _tc) - { - tc = _tc; - } - void process(); //Use this to give data to the decoder. This should be used diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 0df50a85e..ee2799147 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -381,7 +381,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) fpscrMask.n = ones; newVal = (newVal & (uint32_t)fpscrMask) | (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); - tc->getDecodePtr()->setContext(newVal); + tc->getDecoderPtr()->setContext(newVal); } break; case MISCREG_CPSR_Q: -- cgit v1.2.3