From e9c7c8168081e38d272e7c83e7f9503b7e8f162f Mon Sep 17 00:00:00 2001
From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Tue, 19 Feb 2019 09:51:31 +0000
Subject: arch-arm: Expose haveGicv3CPUInterface to the ISA interface

Change-Id: I36232b7618ad875983f34b741c51f12ddb9ae166
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17989
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/arch/arm/isa.cc |  5 ++++-
 src/arch/arm/isa.hh | 12 ++++++++++++
 2 files changed, 16 insertions(+), 1 deletion(-)

(limited to 'src/arch/arm')

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 654608a08..cdc44cdb9 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -65,7 +65,8 @@ ISA::ISA(Params *p)
       _vecRegRenameMode(Enums::Full),
       pmu(p->pmu),
       haveGICv3CPUInterface(false),
-      impdefAsNop(p->impdef_nop)
+      impdefAsNop(p->impdef_nop),
+      afterStartup(false)
 {
     miscRegs[MISCREG_SCTLR_RST] = 0;
 
@@ -406,6 +407,8 @@ ISA::startup(ThreadContext *tc)
             gicv3CpuInterface->setThreadContext(tc);
         }
     }
+
+    afterStartup = true;
 }
 
 
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 1931306f9..b4689d74e 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -105,6 +105,8 @@ namespace ArmISA
          */
         bool impdefAsNop;
 
+        bool afterStartup;
+
         /** MiscReg metadata **/
         struct MiscRegLUTEntry {
             uint32_t lower;  // Lower half mapped to this register
@@ -706,6 +708,16 @@ namespace ArmISA
 
         Enums::DecoderFlavour decoderFlavour() const { return _decoderFlavour; }
 
+        /** Getter for haveGICv3CPUInterface */
+        bool haveGICv3CpuIfc() const
+        {
+            // haveGICv3CPUInterface is initialized at startup time, hence
+            // trying to read its value before the startup stage will lead
+            // to an error
+            assert(afterStartup);
+            return haveGICv3CPUInterface;
+        }
+
         Enums::VecRegRenameMode
         vecRegRenameMode() const
         {
-- 
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