From f54020eb8155371725ab75b0fc5c419287eca084 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Mon, 4 Jun 2018 09:40:19 +0100 Subject: misc: Using smart pointers for memory Requests This patch is changing the underlying type for RequestPtr from Request* to shared_ptr. Having memory requests being managed by smart pointers will simplify the code; it will also prevent memory leakage and dangling pointers. Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3 Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/10996 Reviewed-by: Nikos Nikoleris Maintainer: Nikos Nikoleris --- src/arch/arm/isa.cc | 15 ++++++----- src/arch/arm/locked_mem.hh | 4 +-- src/arch/arm/stage2_lookup.cc | 12 ++++----- src/arch/arm/stage2_lookup.hh | 13 ++++----- src/arch/arm/stage2_mmu.cc | 15 ++++++----- src/arch/arm/stage2_mmu.hh | 18 ++++++------- src/arch/arm/table_walker.cc | 7 ++--- src/arch/arm/table_walker.hh | 3 ++- src/arch/arm/tlb.cc | 27 ++++++++++--------- src/arch/arm/tlb.hh | 51 ++++++++++++++++++++--------------- src/arch/arm/tracers/tarmac_parser.cc | 3 ++- src/arch/arm/tracers/tarmac_parser.hh | 2 +- src/arch/arm/vtophys.cc | 10 +++---- 13 files changed, 100 insertions(+), 80 deletions(-) (limited to 'src/arch/arm') diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index a4e9c7975..aaf209e30 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -1595,16 +1595,20 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) // can't be an atomic translation because that causes problems // with unexpected atomic snoop requests. warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); - Request req(0, val, 0, flags, Request::funcMasterId, - tc->pcState().pc(), tc->contextId()); + + auto req = std::make_shared( + 0, val, 0, flags, Request::funcMasterId, + tc->pcState().pc(), tc->contextId()); + fault = getDTBPtr(tc)->translateFunctional( - &req, tc, mode, tranType); + req, tc, mode, tranType); + TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); HCR hcr = readMiscRegNoEffect(MISCREG_HCR); MiscReg newVal; if (fault == NoFault) { - Addr paddr = req.getPaddr(); + Addr paddr = req->getPaddr(); if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { newVal = (paddr & mask(39, 12)) | @@ -1774,7 +1778,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) case MISCREG_AT_S1E3R_Xt: case MISCREG_AT_S1E3W_Xt: { - RequestPtr req = new Request; + RequestPtr req = std::make_shared(); Request::Flags flags = 0; BaseTLB::Mode mode = BaseTLB::Read; TLB::ArmTranslationType tranType = TLB::NormalTran; @@ -1893,7 +1897,6 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", val, fsr, newVal); } - delete req; setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); return; } diff --git a/src/arch/arm/locked_mem.hh b/src/arch/arm/locked_mem.hh index d33978522..e57ccc9d5 100644 --- a/src/arch/arm/locked_mem.hh +++ b/src/arch/arm/locked_mem.hh @@ -91,7 +91,7 @@ handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask) template inline void -handleLockedRead(XC *xc, RequestPtr req) +handleLockedRead(XC *xc, const RequestPtr &req) { xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr()); xc->setMiscReg(MISCREG_LOCKFLAG, true); @@ -111,7 +111,7 @@ handleLockedSnoopHit(XC *xc) template inline bool -handleLockedWrite(XC *xc, RequestPtr req, Addr cacheBlockMask) +handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask) { if (req->isSwap()) return true; diff --git a/src/arch/arm/stage2_lookup.cc b/src/arch/arm/stage2_lookup.cc index 7e78a3193..e74ec9071 100644 --- a/src/arch/arm/stage2_lookup.cc +++ b/src/arch/arm/stage2_lookup.cc @@ -57,7 +57,7 @@ Fault Stage2LookUp::getTe(ThreadContext *tc, TlbEntry *destTe) { - fault = stage2Tlb->getTE(&stage2Te, &req, tc, mode, this, timing, + fault = stage2Tlb->getTE(&stage2Te, req, tc, mode, this, timing, functional, false, tranType); // Call finish if we're done already if ((fault != NoFault) || (stage2Te != NULL)) { @@ -67,19 +67,19 @@ Stage2LookUp::getTe(ThreadContext *tc, TlbEntry *destTe) // entry is now in the TLB this should always hit the cache. if (fault == NoFault) { if (ELIs64(tc, EL2)) - fault = stage2Tlb->checkPermissions64(stage2Te, &req, mode, tc); + fault = stage2Tlb->checkPermissions64(stage2Te, req, mode, tc); else - fault = stage2Tlb->checkPermissions(stage2Te, &req, mode); + fault = stage2Tlb->checkPermissions(stage2Te, req, mode); } - mergeTe(&req, mode); + mergeTe(req, mode); *destTe = stage1Te; } return fault; } void -Stage2LookUp::mergeTe(RequestPtr req, BaseTLB::Mode mode) +Stage2LookUp::mergeTe(const RequestPtr &req, BaseTLB::Mode mode) { // Check again that we haven't got a fault if (fault == NoFault) { @@ -176,7 +176,7 @@ Stage2LookUp::mergeTe(RequestPtr req, BaseTLB::Mode mode) } void -Stage2LookUp::finish(const Fault &_fault, RequestPtr req, +Stage2LookUp::finish(const Fault &_fault, const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode) { fault = _fault; diff --git a/src/arch/arm/stage2_lookup.hh b/src/arch/arm/stage2_lookup.hh index 870276b0a..8ce3a3a39 100644 --- a/src/arch/arm/stage2_lookup.hh +++ b/src/arch/arm/stage2_lookup.hh @@ -68,13 +68,13 @@ class Stage2LookUp : public BaseTLB::Translation bool functional; TLB::ArmTranslationType tranType; TlbEntry *stage2Te; - Request req; + RequestPtr req; Fault fault; bool complete; bool selfDelete; public: - Stage2LookUp(TLB *s1Tlb, TLB *s2Tlb, TlbEntry s1Te, RequestPtr _req, + Stage2LookUp(TLB *s1Tlb, TLB *s2Tlb, TlbEntry s1Te, const RequestPtr &_req, TLB::Translation *_transState, BaseTLB::Mode _mode, bool _timing, bool _functional, TLB::ArmTranslationType _tranType) : stage1Tlb(s1Tlb), stage2Tlb(s2Tlb), stage1Te(s1Te), s1Req(_req), @@ -82,13 +82,14 @@ class Stage2LookUp : public BaseTLB::Translation functional(_functional), tranType(_tranType), stage2Te(nullptr), fault(NoFault), complete(false), selfDelete(false) { - req.setVirt(0, s1Te.pAddr(s1Req->getVaddr()), s1Req->getSize(), - s1Req->getFlags(), s1Req->masterId(), 0); + req = std::make_shared(); + req->setVirt(0, s1Te.pAddr(s1Req->getVaddr()), s1Req->getSize(), + s1Req->getFlags(), s1Req->masterId(), 0); } Fault getTe(ThreadContext *tc, TlbEntry *destTe); - void mergeTe(RequestPtr req, BaseTLB::Mode mode); + void mergeTe(const RequestPtr &req, BaseTLB::Mode mode); void setSelfDelete() { selfDelete = true; } @@ -96,7 +97,7 @@ class Stage2LookUp : public BaseTLB::Translation void markDelayed() {} - void finish(const Fault &fault, RequestPtr req, ThreadContext *tc, + void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode); }; diff --git a/src/arch/arm/stage2_mmu.cc b/src/arch/arm/stage2_mmu.cc index ba820e339..c6f3ba7c1 100644 --- a/src/arch/arm/stage2_mmu.cc +++ b/src/arch/arm/stage2_mmu.cc @@ -67,17 +67,17 @@ Stage2MMU::readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr, Fault fault; // translate to physical address using the second stage MMU - Request req = Request(); - req.setVirt(0, descAddr, numBytes, flags | Request::PT_WALK, masterId, 0); + auto req = std::make_shared(); + req->setVirt(0, descAddr, numBytes, flags | Request::PT_WALK, masterId, 0); if (isFunctional) { - fault = stage2Tlb()->translateFunctional(&req, tc, BaseTLB::Read); + fault = stage2Tlb()->translateFunctional(req, tc, BaseTLB::Read); } else { - fault = stage2Tlb()->translateAtomic(&req, tc, BaseTLB::Read); + fault = stage2Tlb()->translateAtomic(req, tc, BaseTLB::Read); } // Now do the access. - if (fault == NoFault && !req.getFlags().isSet(Request::NO_ACCESS)) { - Packet pkt = Packet(&req, MemCmd::ReadReq); + if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { + Packet pkt = Packet(req, MemCmd::ReadReq); pkt.dataStatic(data); if (isFunctional) { port.sendFunctional(&pkt); @@ -116,7 +116,8 @@ Stage2MMU::Stage2Translation::Stage2Translation(Stage2MMU &_parent, } void -Stage2MMU::Stage2Translation::finish(const Fault &_fault, RequestPtr req, +Stage2MMU::Stage2Translation::finish(const Fault &_fault, + const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode) { fault = _fault; diff --git a/src/arch/arm/stage2_mmu.hh b/src/arch/arm/stage2_mmu.hh index b01b08153..8787089dc 100644 --- a/src/arch/arm/stage2_mmu.hh +++ b/src/arch/arm/stage2_mmu.hh @@ -70,12 +70,12 @@ class Stage2MMU : public SimObject class Stage2Translation : public BaseTLB::Translation { private: - uint8_t *data; - int numBytes; - Request req; - Event *event; - Stage2MMU &parent; - Addr oVAddr; + uint8_t *data; + int numBytes; + RequestPtr req; + Event *event; + Stage2MMU &parent; + Addr oVAddr; public: Fault fault; @@ -87,18 +87,18 @@ class Stage2MMU : public SimObject markDelayed() {} void - finish(const Fault &fault, RequestPtr req, ThreadContext *tc, + finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode); void setVirt(Addr vaddr, int size, Request::Flags flags, int masterId) { numBytes = size; - req.setVirt(0, vaddr, size, flags, masterId, 0); + req->setVirt(0, vaddr, size, flags, masterId, 0); } void translateTiming(ThreadContext *tc) { - parent.stage2Tlb()->translateTiming(&req, tc, this, BaseTLB::Read); + parent.stage2Tlb()->translateTiming(req, tc, this, BaseTLB::Read); } }; diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc index ba445878b..0668d802a 100644 --- a/src/arch/arm/table_walker.cc +++ b/src/arch/arm/table_walker.cc @@ -184,7 +184,7 @@ TableWalker::drainResume() } Fault -TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint16_t _asid, +TableWalker::walk(const RequestPtr &_req, ThreadContext *_tc, uint16_t _asid, uint8_t _vmid, bool _isHyp, TLB::Mode _mode, TLB::Translation *_trans, bool _timing, bool _functional, bool secure, TLB::ArmTranslationType tranType, @@ -2021,13 +2021,14 @@ TableWalker::fetchDescriptor(Addr descAddr, uint8_t *data, int numBytes, currState->tc->getCpuPtr()->clockPeriod(), flags); (this->*doDescriptor)(); } else { - RequestPtr req = new Request(descAddr, numBytes, flags, masterId); + RequestPtr req = std::make_shared( + descAddr, numBytes, flags, masterId); + req->taskId(ContextSwitchTaskId::DMA); PacketPtr pkt = new Packet(req, MemCmd::ReadReq); pkt->dataStatic(data); port->sendFunctional(pkt); (this->*doDescriptor)(); - delete req; delete pkt; } } diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh index 1957bef0d..57e3aed06 100644 --- a/src/arch/arm/table_walker.hh +++ b/src/arch/arm/table_walker.hh @@ -894,7 +894,8 @@ class TableWalker : public MemObject void regStats() override; - Fault walk(RequestPtr req, ThreadContext *tc, uint16_t asid, uint8_t _vmid, + Fault walk(const RequestPtr &req, ThreadContext *tc, + uint16_t asid, uint8_t _vmid, bool _isHyp, TLB::Mode mode, TLB::Translation *_trans, bool timing, bool functional, bool secure, TLB::ArmTranslationType tranType, bool _stage2Req); diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index 192f01bce..d2153e779 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -133,7 +133,8 @@ TLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa) } Fault -TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const +TLB::finalizePhysical(const RequestPtr &req, + ThreadContext *tc, Mode mode) const { const Addr paddr = req->getPaddr(); @@ -561,7 +562,7 @@ TLB::regProbePoints() } Fault -TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, +TLB::translateSe(const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool &delay, bool timing) { updateMiscReg(tc); @@ -601,7 +602,7 @@ TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, } Fault -TLB::checkPermissions(TlbEntry *te, RequestPtr req, Mode mode) +TLB::checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode) { // a data cache maintenance instruction that operates by MVA does // not generate a Data Abort exeception due to a Permission fault @@ -779,7 +780,7 @@ TLB::checkPermissions(TlbEntry *te, RequestPtr req, Mode mode) Fault -TLB::checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode, +TLB::checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode, ThreadContext *tc) { assert(aarch64); @@ -989,7 +990,7 @@ TLB::checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode, } Fault -TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, +TLB::translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool &delay, bool timing, TLB::ArmTranslationType tranType, bool functional) { @@ -1158,7 +1159,7 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, } Fault -TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode, +TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode, TLB::ArmTranslationType tranType) { updateMiscReg(tc, tranType); @@ -1179,7 +1180,7 @@ TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode, } Fault -TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode, +TLB::translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode, TLB::ArmTranslationType tranType) { updateMiscReg(tc, tranType); @@ -1200,7 +1201,7 @@ TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode, } void -TLB::translateTiming(RequestPtr req, ThreadContext *tc, +TLB::translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, TLB::ArmTranslationType tranType) { updateMiscReg(tc, tranType); @@ -1217,7 +1218,7 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc, } Fault -TLB::translateComplete(RequestPtr req, ThreadContext *tc, +TLB::translateComplete(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, TLB::ArmTranslationType tranType, bool callFromS2) { @@ -1404,7 +1405,7 @@ TLB::tranTypeEL(CPSR cpsr, ArmTranslationType type) } Fault -TLB::getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, +TLB::getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, bool is_secure, TLB::ArmTranslationType tranType) { @@ -1466,7 +1467,8 @@ TLB::getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, } Fault -TLB::getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, +TLB::getResultTe(TlbEntry **te, const RequestPtr &req, + ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, TlbEntry *mergeTe) { @@ -1549,7 +1551,8 @@ TLB::setTestInterface(SimObject *_ti) } Fault -TLB::testTranslation(RequestPtr req, Mode mode, TlbEntry::DomainType domain) +TLB::testTranslation(const RequestPtr &req, Mode mode, + TlbEntry::DomainType domain) { if (!test || !req->hasSize() || req->getSize() == 0 || req->isCacheMaintenance()) { diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh index b8ea99054..336b31b78 100644 --- a/src/arch/arm/tlb.hh +++ b/src/arch/arm/tlb.hh @@ -77,7 +77,7 @@ class TlbTestInterface * @param mode Access type * @param domain Domain type */ - virtual Fault translationCheck(RequestPtr req, bool is_priv, + virtual Fault translationCheck(const RequestPtr &req, bool is_priv, BaseTLB::Mode mode, TlbEntry::DomainType domain) = 0; @@ -227,16 +227,18 @@ class TLB : public BaseTLB void insert(Addr vaddr, TlbEntry &pte); - Fault getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, + Fault getTE(TlbEntry **te, const RequestPtr &req, + ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, bool is_secure, ArmTranslationType tranType); - Fault getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc, - Mode mode, Translation *translation, bool timing, + Fault getResultTe(TlbEntry **te, const RequestPtr &req, + ThreadContext *tc, Mode mode, + Translation *translation, bool timing, bool functional, TlbEntry *mergeTe); - Fault checkPermissions(TlbEntry *te, RequestPtr req, Mode mode); - Fault checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode, + Fault checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode); + Fault checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode, ThreadContext *tc); @@ -292,9 +294,13 @@ class TLB : public BaseTLB */ void flushIpaVmid(Addr ipa, bool secure_lookup, bool hyp, uint8_t target_el); - Fault trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain); - Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec, - bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level); + Fault trickBoxCheck(const RequestPtr &req, Mode mode, + TlbEntry::DomainType domain); + + Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, + bool is_exec, bool is_write, + TlbEntry::DomainType domain, + LookupLevel lookup_level); void printTlb() const; @@ -318,10 +324,11 @@ class TLB : public BaseTLB * Do a functional lookup on the TLB (for checker cpu) that * behaves like a normal lookup without modifying any page table state. */ - Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode, - ArmTranslationType tranType); + Fault translateFunctional(const RequestPtr &req, ThreadContext *tc, + Mode mode, ArmTranslationType tranType); Fault - translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) override + translateFunctional(const RequestPtr &req, + ThreadContext *tc, Mode mode) override { return translateFunctional(req, tc, mode, NormalTran); } @@ -340,33 +347,35 @@ class TLB : public BaseTLB return _attr; } - Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode, + Fault translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool &delay, bool timing, ArmTranslationType tranType, bool functional = false); - Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode, + Fault translateSe(const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool &delay, bool timing); - Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode, + Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode, ArmTranslationType tranType); Fault - translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) override + translateAtomic(const RequestPtr &req, + ThreadContext *tc, Mode mode) override { return translateAtomic(req, tc, mode, NormalTran); } void translateTiming( - RequestPtr req, ThreadContext *tc, + const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, ArmTranslationType tranType); void - translateTiming(RequestPtr req, ThreadContext *tc, + translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode) override { translateTiming(req, tc, translation, mode, NormalTran); } - Fault translateComplete(RequestPtr req, ThreadContext *tc, + Fault translateComplete(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, ArmTranslationType tranType, bool callFromS2); Fault finalizePhysical( - RequestPtr req, ThreadContext *tc, Mode mode) const override; + const RequestPtr &req, + ThreadContext *tc, Mode mode) const override; void drainResume() override; @@ -446,7 +455,7 @@ private: bool checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el); public: /* Testing */ - Fault testTranslation(RequestPtr req, Mode mode, + Fault testTranslation(const RequestPtr &req, Mode mode, TlbEntry::DomainType domain); Fault testWalk(Addr pa, Addr size, Addr va, bool is_secure, Mode mode, TlbEntry::DomainType domain, diff --git a/src/arch/arm/tracers/tarmac_parser.cc b/src/arch/arm/tracers/tarmac_parser.cc index ab19dd38a..68738cba2 100644 --- a/src/arch/arm/tracers/tarmac_parser.cc +++ b/src/arch/arm/tracers/tarmac_parser.cc @@ -764,6 +764,7 @@ TarmacParserRecord::TarmacParserRecord(Tick _when, ThreadContext *_thread, parsingStarted(false), mismatch(false), mismatchOnPcOrOpcode(false), parent(_parent) { + memReq = std::make_shared(); } void @@ -1048,7 +1049,7 @@ bool TarmacParserRecord::readMemNoEffect(Addr addr, uint8_t *data, unsigned size, unsigned flags) { - Request* req = &memReq; + const RequestPtr &req = memReq; TheISA::TLB* dtb = static_cast(thread->getDTBPtr()); req->setVirt(0, addr, size, flags, thread->pcState().instAddr(), diff --git a/src/arch/arm/tracers/tarmac_parser.hh b/src/arch/arm/tracers/tarmac_parser.hh index 7e6a780a0..6acdd627e 100644 --- a/src/arch/arm/tracers/tarmac_parser.hh +++ b/src/arch/arm/tracers/tarmac_parser.hh @@ -197,7 +197,7 @@ class TarmacParserRecord : public TarmacBaseRecord bool mismatchOnPcOrOpcode; /** Request for memory write checks. */ - Request memReq; + RequestPtr memReq; protected: TarmacParser& parent; diff --git a/src/arch/arm/vtophys.cc b/src/arch/arm/vtophys.cc index 872867819..3a6731541 100644 --- a/src/arch/arm/vtophys.cc +++ b/src/arch/arm/vtophys.cc @@ -70,7 +70,7 @@ try_translate(ThreadContext *tc, Addr addr) Fault fault; // Set up a functional memory Request to pass to the TLB // to get it to translate the vaddr to a paddr - Request req(0, addr, 64, 0x40, -1, 0, 0); + auto req = std::make_shared(0, addr, 64, 0x40, -1, 0, 0); ArmISA::TLB *tlb; // Check the TLBs for a translation @@ -81,14 +81,14 @@ try_translate(ThreadContext *tc, Addr addr) // Calling translateFunctional invokes a table-walk if required // so we should always succeed tlb = static_cast(tc->getDTBPtr()); - fault = tlb->translateFunctional(&req, tc, BaseTLB::Read, TLB::NormalTran); + fault = tlb->translateFunctional(req, tc, BaseTLB::Read, TLB::NormalTran); if (fault == NoFault) - return std::make_pair(true, req.getPaddr()); + return std::make_pair(true, req->getPaddr()); tlb = static_cast(tc->getITBPtr()); - fault = tlb->translateFunctional(&req, tc, BaseTLB::Read, TLB::NormalTran); + fault = tlb->translateFunctional(req, tc, BaseTLB::Read, TLB::NormalTran); if (fault == NoFault) - return std::make_pair(true, req.getPaddr()); + return std::make_pair(true, req->getPaddr()); return std::make_pair(false, 0); } -- cgit v1.2.3