From 5e8287d2e2eaf058495442ea9e32fafc343a0b53 Mon Sep 17 00:00:00 2001 From: Nathanael Premillieu Date: Wed, 5 Apr 2017 12:46:06 -0500 Subject: arch, cpu: Architectural Register structural indexing Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/2700 --- src/arch/generic/types.hh | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/arch/generic/types.hh') diff --git a/src/arch/generic/types.hh b/src/arch/generic/types.hh index 78ead6832..bb6eafd66 100644 --- a/src/arch/generic/types.hh +++ b/src/arch/generic/types.hh @@ -37,6 +37,9 @@ #include "base/types.hh" #include "sim/serialize.hh" +// Logical register index type. +typedef uint16_t RegIndex; + namespace GenericISA { -- cgit v1.2.3