From ae390c629f2a10fd6a1c2eb50b7d3510d6e091da Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 2 Sep 2019 21:26:12 -0700 Subject: arch: Make a base class for Interrupts. That abstracts the ISA further from the CPU, getting us a small step closer to being able to build in more than one ISA at a time. Change-Id: Ibf7e26a3df411ffe994ac1e11d2a53b656863223 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20831 Tested-by: kokoro Reviewed-by: Jason Lowe-Power Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg --- src/arch/generic/BaseInterrupts.py | 34 +++++++++++++ src/arch/generic/SConscript | 1 + src/arch/generic/interrupts.hh | 98 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 133 insertions(+) create mode 100644 src/arch/generic/BaseInterrupts.py create mode 100644 src/arch/generic/interrupts.hh (limited to 'src/arch/generic') diff --git a/src/arch/generic/BaseInterrupts.py b/src/arch/generic/BaseInterrupts.py new file mode 100644 index 000000000..b373d80bc --- /dev/null +++ b/src/arch/generic/BaseInterrupts.py @@ -0,0 +1,34 @@ +# Copyright 2019 Google, Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +from m5.params import * +from m5.SimObject import SimObject + +class BaseInterrupts(SimObject): + type = 'BaseInterrupts' + abstract = True + cxx_header = "arch/generic/interrupts.hh" diff --git a/src/arch/generic/SConscript b/src/arch/generic/SConscript index 0fc5e7402..61034bfe9 100644 --- a/src/arch/generic/SConscript +++ b/src/arch/generic/SConscript @@ -46,6 +46,7 @@ if env['TARGET_ISA'] == 'null': Source('decode_cache.cc') Source('mmapped_ipr.cc') +SimObject('BaseInterrupts.py') SimObject('BaseTLB.py') SimObject('ISACommon.py') diff --git a/src/arch/generic/interrupts.hh b/src/arch/generic/interrupts.hh new file mode 100644 index 000000000..cae2d0911 --- /dev/null +++ b/src/arch/generic/interrupts.hh @@ -0,0 +1,98 @@ +/* + * Copyright 2019 Google, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_GENERIC_INTERRUPTS_HH__ +#define __ARCH_GENERIC_INTERRUPTS_HH__ + +#include "params/BaseInterrupts.hh" +#include "sim/sim_object.hh" + +class ThreadContext; +class BaseCPU; + +class BaseInterrupts : public SimObject +{ + protected: + BaseCPU *cpu; + + public: + typedef BaseInterruptsParams Params; + + BaseInterrupts(Params *p) : SimObject(p) {} + + virtual void setCPU(BaseCPU * newCPU) = 0; + + const Params * + params() const + { + return dynamic_cast(_params); + } + + /* + * Functions for retrieving interrupts for the CPU to handle. + */ + + /* + * Return whether there are any interrupts waiting to be recognized. + */ + virtual bool checkInterrupts(ThreadContext *tc) const = 0; + /* + * Return an interrupt to process. This should return an interrupt exactly + * when checkInterrupts returns true. + */ + virtual Fault getInterrupt(ThreadContext *tc) = 0; + /* + * Update interrupt related state after an interrupt has been processed. + */ + virtual void updateIntrInfo(ThreadContext *tc) = 0; + + /* + * Old functions needed for compatability but which will be phased out + * eventually. + */ + virtual void + post(int int_num, int index) + { + panic("Interrupts::post unimplemented!\n"); + } + + virtual void + clear(int int_num, int index) + { + panic("Interrupts::clear unimplemented!\n"); + } + + virtual void + clearAll() + { + panic("Interrupts::clearAll unimplemented!\n"); + } +}; + +#endif // __ARCH_GENERIC_INTERRUPTS_HH__ -- cgit v1.2.3