From f54020eb8155371725ab75b0fc5c419287eca084 Mon Sep 17 00:00:00 2001
From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Mon, 4 Jun 2018 09:40:19 +0100
Subject: misc: Using smart pointers for memory Requests

This patch is changing the underlying type for RequestPtr from Request*
to shared_ptr<Request>. Having memory requests being managed by smart
pointers will simplify the code; it will also prevent memory leakage and
dangling pointers.

Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10996
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
---
 src/arch/generic/locked_mem.hh |  4 ++--
 src/arch/generic/tlb.cc        |  7 ++++---
 src/arch/generic/tlb.hh        | 16 ++++++++--------
 3 files changed, 14 insertions(+), 13 deletions(-)

(limited to 'src/arch/generic')

diff --git a/src/arch/generic/locked_mem.hh b/src/arch/generic/locked_mem.hh
index f6537995b..a7e517bb1 100644
--- a/src/arch/generic/locked_mem.hh
+++ b/src/arch/generic/locked_mem.hh
@@ -63,7 +63,7 @@ handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
 
 template <class XC>
 inline void
-handleLockedRead(XC *xc, RequestPtr req)
+handleLockedRead(XC *xc, const RequestPtr &req)
 {
 }
 
@@ -76,7 +76,7 @@ handleLockedSnoopHit(XC *xc)
 
 template <class XC>
 inline bool
-handleLockedWrite(XC *xc, RequestPtr req, Addr cacheBlockMask)
+handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
 {
     return true;
 }
diff --git a/src/arch/generic/tlb.cc b/src/arch/generic/tlb.cc
index 807f06dab..aebdd4bfe 100644
--- a/src/arch/generic/tlb.cc
+++ b/src/arch/generic/tlb.cc
@@ -37,7 +37,7 @@
 #include "sim/process.hh"
 
 Fault
-GenericTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode)
+GenericTLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode)
 {
     if (FullSystem)
         panic("Generic translation shouldn't be used in full system mode.\n");
@@ -52,7 +52,7 @@ GenericTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode)
 }
 
 void
-GenericTLB::translateTiming(RequestPtr req, ThreadContext *tc,
+GenericTLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
         Translation *translation, Mode mode)
 {
     assert(translation);
@@ -60,7 +60,8 @@ GenericTLB::translateTiming(RequestPtr req, ThreadContext *tc,
 }
 
 Fault
-GenericTLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
+GenericTLB::finalizePhysical(const RequestPtr &req, ThreadContext *tc,
+                             Mode mode) const
 {
     return NoFault;
 }
diff --git a/src/arch/generic/tlb.hh b/src/arch/generic/tlb.hh
index e0becf727..89180341c 100644
--- a/src/arch/generic/tlb.hh
+++ b/src/arch/generic/tlb.hh
@@ -77,7 +77,7 @@ class BaseTLB : public SimObject
          * be responsible for cleaning itself up which will happen in this
          * function. Once it's called, the object is no longer valid.
          */
-        virtual void finish(const Fault &fault, RequestPtr req,
+        virtual void finish(const Fault &fault, const RequestPtr &req,
                             ThreadContext *tc, Mode mode) = 0;
 
         /** This function is used by the page table walker to determine if it
@@ -92,12 +92,12 @@ class BaseTLB : public SimObject
     virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
 
     virtual Fault translateAtomic(
-            RequestPtr req, ThreadContext *tc, Mode mode) = 0;
+            const RequestPtr &req, ThreadContext *tc, Mode mode) = 0;
     virtual void translateTiming(
-            RequestPtr req, ThreadContext *tc,
+            const RequestPtr &req, ThreadContext *tc,
             Translation *translation, Mode mode) = 0;
     virtual Fault
-    translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
+    translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode)
     {
         panic("Not implemented.\n");
     }
@@ -117,7 +117,7 @@ class BaseTLB : public SimObject
      * @return A fault on failure, NoFault otherwise.
      */
     virtual Fault finalizePhysical(
-            RequestPtr req, ThreadContext *tc, Mode mode) const = 0;
+            const RequestPtr &req, ThreadContext *tc, Mode mode) const = 0;
 
     /**
      * Remove all entries from the TLB
@@ -154,13 +154,13 @@ class GenericTLB : public BaseTLB
     void demapPage(Addr vaddr, uint64_t asn) override;
 
     Fault translateAtomic(
-        RequestPtr req, ThreadContext *tc, Mode mode) override;
+        const RequestPtr &req, ThreadContext *tc, Mode mode) override;
     void translateTiming(
-        RequestPtr req, ThreadContext *tc,
+        const RequestPtr &req, ThreadContext *tc,
         Translation *translation, Mode mode) override;
 
     Fault finalizePhysical(
-        RequestPtr req, ThreadContext *tc, Mode mode) const override;
+        const RequestPtr &req, ThreadContext *tc, Mode mode) const override;
 };
 
 #endif // __ARCH_GENERIC_TLB_HH__
-- 
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