From f6b828d068b046df17b462a4d05af957c038a3a8 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sat, 6 Feb 2016 17:21:20 -0800 Subject: style: eliminate explicit boolean comparisons Result of running 'hg m5style --skip-all --fix-control -a' to get rid of '== true' comparisons, plus trivial manual edits to get rid of '== false'/'== False' comparisons. Left a couple of explicit comparisons in where they didn't seem unreasonable: invalid boolean comparison in src/arch/mips/interrupts.cc:155 >> DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc) == true\n");<< invalid boolean comparison in src/unittest/unittest.hh:110 >> "EXPECT_FALSE(" #expr ")", (expr) == false)<< --- src/arch/hsail/insts/decl.hh | 12 ++++++------ src/arch/hsail/insts/mem.hh | 2 +- 2 files changed, 7 insertions(+), 7 deletions(-) (limited to 'src/arch/hsail/insts') diff --git a/src/arch/hsail/insts/decl.hh b/src/arch/hsail/insts/decl.hh index e2da501b9..90609c365 100644 --- a/src/arch/hsail/insts/decl.hh +++ b/src/arch/hsail/insts/decl.hh @@ -189,7 +189,7 @@ namespace HsailISA int numSrcRegOperands() { int operands = 0; for (int i = 0; i < NumSrcOperands; i++) { - if (src[i].isVectorRegister() == true) { + if (src[i].isVectorRegister()) { operands++; } } @@ -325,13 +325,13 @@ namespace HsailISA int numSrcRegOperands() { int operands = 0; - if (src0.isVectorRegister() == true) { + if (src0.isVectorRegister()) { operands++; } - if (src1.isVectorRegister() == true) { + if (src1.isVectorRegister()) { operands++; } - if (src2.isVectorRegister() == true) { + if (src2.isVectorRegister()) { operands++; } return operands; @@ -485,10 +485,10 @@ namespace HsailISA int numSrcRegOperands() { int operands = 0; - if (src0.isVectorRegister() == true) { + if (src0.isVectorRegister()) { operands++; } - if (src1.isVectorRegister() == true) { + if (src1.isVectorRegister()) { operands++; } return operands; diff --git a/src/arch/hsail/insts/mem.hh b/src/arch/hsail/insts/mem.hh index d3ce76dee..c3b3bd4f9 100644 --- a/src/arch/hsail/insts/mem.hh +++ b/src/arch/hsail/insts/mem.hh @@ -1239,7 +1239,7 @@ namespace HsailISA { int operands = 0; for (int i = 0; i < NumSrcOperands; i++) { - if (src[i].isVectorRegister() == true) { + if (src[i].isVectorRegister()) { operands++; } } -- cgit v1.2.3