From c6d137f5655dec978e1555e17e3a850f88a541c4 Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Fri, 22 Jun 2007 20:09:46 -0400 Subject: add Control Bitfield class --HG-- extra : convert_revision : 31e7243c8820cb9f6744c53c417460dee9adaf44 --- src/arch/isa_parser.py | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'src/arch/isa_parser.py') diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py index 7edb9f3d7..95c57af2f 100755 --- a/src/arch/isa_parser.py +++ b/src/arch/isa_parser.py @@ -25,6 +25,7 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # Authors: Steve Reinhardt +# Gabe Black # Korey Sewell import os @@ -1410,6 +1411,25 @@ class ControlRegOperand(Operand): error(0, 'Attempt to write control register as FP') wb = 'xc->setMiscRegOperand(this, %s, %s);\n' % \ (self.dest_reg_idx, self.base_name) + +class ControlBitfieldOperand(ControlRegOperand): + def makeRead(self): + bit_select = 0 + if (self.ctype == 'float' or self.ctype == 'double'): + error(0, 'Attempt to read control register as FP') + base = 'xc->readMiscReg(%s)' % self.reg_spec + name = self.base_name + return '%s = bits(%s, %s_HI, %s_LO);' % \ + (name, base, name, name) + + def makeWrite(self): + if (self.ctype == 'float' or self.ctype == 'double'): + error(0, 'Attempt to write control register as FP') + base = 'xc->readMiscReg(%s)' % self.reg_spec + name = self.base_name + wb_val = 'insertBits(%s, %s_HI, %s_LO, %s)' % \ + (base, name, name, self.base_name) + wb = 'xc->setMiscRegOperand(this, %s, %s );\n' % (self.dest_reg_idx, wb_val) wb += 'if (traceData) { traceData->setData(%s); }' % \ self.base_name return wb -- cgit v1.2.3 From ac19e0c5050219cbb0579a319fa3fab5cf92835d Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Fri, 22 Jun 2007 21:09:35 -0400 Subject: FINISH off merge of mips mt/dsp isa extensions by adding the ControlBitfieldOPerand to ISA Parser. Now, while things do build, we have to fix broken functionality... src/arch/isa_parser.py: add back deleted writeback in Control Operand --HG-- extra : convert_revision : dba11af220a1281fa53f79d87e4f8752bdfc56db --- src/arch/isa_parser.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/arch/isa_parser.py') diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py index 95c57af2f..754a64fdb 100755 --- a/src/arch/isa_parser.py +++ b/src/arch/isa_parser.py @@ -25,7 +25,6 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # Authors: Steve Reinhardt -# Gabe Black # Korey Sewell import os @@ -1411,6 +1410,9 @@ class ControlRegOperand(Operand): error(0, 'Attempt to write control register as FP') wb = 'xc->setMiscRegOperand(this, %s, %s);\n' % \ (self.dest_reg_idx, self.base_name) + wb += 'if (traceData) { traceData->setData(%s); }' % \ + self.base_name + return wb class ControlBitfieldOperand(ControlRegOperand): def makeRead(self): -- cgit v1.2.3