From 6c72c3551978ef2eabbe9727bf24fd2fcf385318 Mon Sep 17 00:00:00 2001 From: Fernando Endo Date: Sat, 15 Oct 2016 14:58:45 -0500 Subject: cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass Modify the opClass assigned to AArch64 FP instructions from SimdFloat* to Float*. Also create the FloatMemRead and FloatMemWrite opClasses, which distinguishes writes to the INT and FP register banks. Change the latency of (Simd)FloatMultAcc to 5, based on the Cortex-A72, where the "latency" of FMADD is 3 if the next instruction is a FMADD and has only the augend to destination dependency, otherwise it's 7 cycles. Signed-off-by: Jason Lowe-Power --- src/arch/isa_parser.py | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) (limited to 'src/arch/isa_parser.py') diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py index 749eaf88d..8d609ae5f 100755 --- a/src/arch/isa_parser.py +++ b/src/arch/isa_parser.py @@ -1130,9 +1130,21 @@ class InstObjParams(object): # These are good enough for most cases. if not self.op_class: if 'IsStore' in self.flags: - self.op_class = 'MemWriteOp' + # The order matters here: 'IsFloating' and 'IsInteger' are + # usually set in FP instructions because of the base + # register + if 'IsFloating' in self.flags: + self.op_class = 'FloatMemWriteOp' + else: + self.op_class = 'MemWriteOp' elif 'IsLoad' in self.flags or 'IsPrefetch' in self.flags: - self.op_class = 'MemReadOp' + # The order matters here: 'IsFloating' and 'IsInteger' are + # usually set in FP instructions because of the base + # register + if 'IsFloating' in self.flags: + self.op_class = 'FloatMemReadOp' + else: + self.op_class = 'MemReadOp' elif 'IsFloating' in self.flags: self.op_class = 'FloatAddOp' else: -- cgit v1.2.3