From 95561dc138243b1fda266ed4ef4ffdc64700c353 Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Wed, 26 Jul 2006 18:47:06 -0400 Subject: MIPS ISA runs 'hello world' in O3CPU ... src/arch/mips/isa/base.isa: special case syscall disasembly... maybe give own instruction class? src/arch/mips/isa/decoder.isa: add 'IsSerializeAfter' flag for syscall src/cpu/o3/commit.hh: Add skidBuffer to commit src/cpu/o3/commit_impl.hh: Use skidbuffer in MIPS ISA src/cpu/o3/fetch_impl.hh: Print name out when there is a fault src/cpu/o3/mips/cpu_impl.hh: change comment --HG-- extra : convert_revision : d032549e07102bdd50aa09f044fce8de6f0239b5 --- src/arch/mips/isa/base.isa | 32 +++++++++++++++++++------------- 1 file changed, 19 insertions(+), 13 deletions(-) (limited to 'src/arch/mips/isa/base.isa') diff --git a/src/arch/mips/isa/base.isa b/src/arch/mips/isa/base.isa index f07b06e03..7c042f16f 100644 --- a/src/arch/mips/isa/base.isa +++ b/src/arch/mips/isa/base.isa @@ -79,21 +79,27 @@ output decoder {{ ccprintf(ss, "%-10s ", mnemonic); - if(_numDestRegs > 0){ - printReg(ss, _destRegIdx[0]); + // Need to find standard way to not print + // this info. Maybe add bool variable to + // class? + if (mnemonic != "syscall") { + if(_numDestRegs > 0){ + printReg(ss, _destRegIdx[0]); + } + + if(_numSrcRegs > 0) { + ss << ", "; + printReg(ss, _srcRegIdx[0]); + } + + if(_numSrcRegs > 1) { + ss << ", "; + printReg(ss, _srcRegIdx[1]); + } } - if(_numSrcRegs > 0) { - ss << ", "; - printReg(ss, _srcRegIdx[0]); - } - - if(_numSrcRegs > 1) { - ss << ", "; - printReg(ss, _srcRegIdx[1]); - } - - + // Should we define a separate inst. class + // just for two insts? if(mnemonic == "sll" || mnemonic == "sra"){ ccprintf(ss,", %d",SA); } -- cgit v1.2.3