From 6c046a28dc6624f57655e5106568721972cbae1e Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Mon, 6 Oct 2008 02:07:04 -0400 Subject: fix shadow set bugs in MIPS code that caused out of bounds access... panic rdpgpr/wrpgpr instructions until a better impl. of MIPS shadow sets is available. --- src/arch/mips/isa/decoder.isa | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'src/arch/mips/isa/decoder.isa') diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa index 0a12c4f6e..8af504e55 100644 --- a/src/arch/mips/isa/decoder.isa +++ b/src/arch/mips/isa/decoder.isa @@ -603,7 +603,8 @@ decode OPCODE_HI default Unknown::unknown() { 0xA: rdpgpr({{ if(Config_AR >= 1) { // Rev 2 of the architecture - Rd = xc->tcBase()->readIntReg(RT + NumIntRegs * SRSCtl_PSS); + panic("Shadow Sets Not Fully Implemented.\n"); + //Rd = xc->tcBase()->readIntReg(RT + NumIntRegs * SRSCtl_PSS); } else { @@ -613,7 +614,8 @@ decode OPCODE_HI default Unknown::unknown() { 0xE: wrpgpr({{ if(Config_AR >= 1) { // Rev 2 of the architecture - xc->tcBase()->setIntReg(RD + NumIntRegs * SRSCtl_PSS,Rt); + panic("Shadow Sets Not Fully Implemented.\n"); + //xc->tcBase()->setIntReg(RD + NumIntRegs * SRSCtl_PSS,Rt); // warn("Writing %d to %d, PSS: %d, SRS: %x\n",Rt,RD + NumIntRegs * SRSCtl_PSS, SRSCtl_PSS,SRSCtl); } else -- cgit v1.2.3