From 35e20c7470a16cbc1187553375269800b980eb78 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Fri, 30 Sep 2011 00:27:16 -0700
Subject: SE/FS: Use the new FullSystem constant where possible.

---
 src/arch/mips/isa/formats/control.isa | 8 ++++----
 src/arch/mips/isa/formats/dsp.isa     | 4 ++--
 src/arch/mips/isa/formats/fp.isa      | 4 ++--
 src/arch/mips/isa/formats/unimp.isa   | 6 +++---
 4 files changed, 11 insertions(+), 11 deletions(-)

(limited to 'src/arch/mips/isa/formats')

diff --git a/src/arch/mips/isa/formats/control.isa b/src/arch/mips/isa/formats/control.isa
index 7e90ed3e5..2d6748c05 100644
--- a/src/arch/mips/isa/formats/control.isa
+++ b/src/arch/mips/isa/formats/control.isa
@@ -128,7 +128,7 @@ def template ControlTLBExecute {{
             %(op_decl)s;
             %(op_rd)s;
 
-            if (FULL_SYSTEM) {
+            if (FullSystem) {
                 if (isCoprocessor0Enabled(xc)) {
                     if(isMMUTLB(xc)){
                         %(code)s;
@@ -176,7 +176,7 @@ output exec {{
         bool
         isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
         {
-            if (!FULL_SYSTEM)
+            if (!FullSystem)
                 return true;
 
             MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
@@ -198,7 +198,7 @@ output exec {{
         bool inline
         isCoprocessor0Enabled(%(CPU_exec_context)s *xc)
         {
-            if (FULL_SYSTEM) {
+            if (FullSystem) {
                 MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
                 MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
                 // In Stat, EXL, ERL or CU0 set, CP0 accessible
@@ -215,7 +215,7 @@ output exec {{
         isMMUTLB(%(CPU_exec_context)s *xc)
         {
             MiscReg Config = xc->readMiscReg(MISCREG_CONFIG);
-            return FULL_SYSTEM && (Config & 0x380) == 0x80;
+            return FullSystem && (Config & 0x380) == 0x80;
         }
 }};
 
diff --git a/src/arch/mips/isa/formats/dsp.isa b/src/arch/mips/isa/formats/dsp.isa
index 2eeefe806..b288b7b20 100755
--- a/src/arch/mips/isa/formats/dsp.isa
+++ b/src/arch/mips/isa/formats/dsp.isa
@@ -143,7 +143,7 @@ output exec {{
     bool
     isDspEnabled(%(CPU_exec_context)s *xc)
     {
-        return !FULL_SYSTEM || bits(xc->readMiscReg(MISCREG_STATUS), 24);
+        return !FullSystem || bits(xc->readMiscReg(MISCREG_STATUS), 24);
     }
 }};
 
@@ -151,7 +151,7 @@ output exec {{
     bool
     isDspPresent(%(CPU_exec_context)s *xc)
     {
-        return !FULL_SYSTEM || bits(xc->readMiscReg(MISCREG_CONFIG3), 10);
+        return !FullSystem || bits(xc->readMiscReg(MISCREG_CONFIG3), 10);
     }
 }};
 
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa
index f99d2327e..63823f404 100644
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -174,7 +174,7 @@ def template FloatingPointExecute {{
 
                 //When is the right time to reset cause bits?
                 //start of every instruction or every cycle?
-                if (FULL_SYSTEM)
+                if (FullSystem)
                     fpResetCauseBits(xc);
                 %(op_decl)s;
                 %(op_rd)s;
@@ -191,7 +191,7 @@ def template FloatingPointExecute {{
                     //Check for IEEE 754 FP Exceptions
                     //fault = fpNanOperands((FPOp*)this, xc, Fd, traceData);
                     bool invalid_op = false;
-                    if (FULL_SYSTEM) {
+                    if (FullSystem) {
                         invalid_op =
                             fpInvalidOp((FPOp*)this, xc, Fd, traceData);
                     }
diff --git a/src/arch/mips/isa/formats/unimp.isa b/src/arch/mips/isa/formats/unimp.isa
index 65b4425af..d567a113f 100644
--- a/src/arch/mips/isa/formats/unimp.isa
+++ b/src/arch/mips/isa/formats/unimp.isa
@@ -193,7 +193,7 @@ output exec {{
     CP0Unimplemented::execute(%(CPU_exec_context)s *xc,
                                Trace::InstRecord *traceData) const
     {
-        if (FULL_SYSTEM) {
+        if (FullSystem) {
             if (!isCoprocessorEnabled(xc, 0))
                 return new CoprocessorUnusableFault(0);
             else
@@ -210,7 +210,7 @@ output exec {{
     CP1Unimplemented::execute(%(CPU_exec_context)s *xc,
                                Trace::InstRecord *traceData) const
     {
-        if (FULL_SYSTEM) {
+        if (FullSystem) {
             if (!isCoprocessorEnabled(xc, 1))
                 return new CoprocessorUnusableFault(1);
             else
@@ -227,7 +227,7 @@ output exec {{
     CP2Unimplemented::execute(%(CPU_exec_context)s *xc,
                                Trace::InstRecord *traceData) const
     {
-        if (FULL_SYSTEM) {
+        if (FullSystem) {
             if (!isCoprocessorEnabled(xc, 2))
                 return new CoprocessorUnusableFault(2);
             else
-- 
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