From d735abe5dabf483aafb0ccfb0a70cb7c3b0a5a74 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Mon, 31 Oct 2011 01:09:44 -0700
Subject: GCC: Get everything working with gcc 4.6.1.

And by "everything" I mean all the quick regressions.
---
 src/arch/mips/isa/decoder.isa    |  8 +++-----
 src/arch/mips/isa/formats/mt.isa | 22 ++++++----------------
 src/arch/mips/isa/includes.isa   |  2 ++
 3 files changed, 11 insertions(+), 21 deletions(-)

(limited to 'src/arch/mips/isa')

diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 7b8dafdba..179e409dd 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -497,8 +497,8 @@ decode OPCODE_HI default Unknown::unknown() {
                             0x2: mttc1({{
                                 uint64_t data = xc->readRegOtherThread(RD +
                                                                        FP_Base_DepTag);
-                                data = insertBits(data, top_bit,
-                                                  bottom_bit, Rt);
+                                data = insertBits(data, MT_H ? 63 : 31,
+                                                  MT_H ? 32 : 0, Rt);
                                 xc->setRegOtherThread(RD + FP_Base_DepTag,
                                                       data);
                             }});
@@ -532,7 +532,7 @@ decode OPCODE_HI default Unknown::unknown() {
                                     panic("FP Control Value (%d) "
                                             "Not Available. Ignoring "
                                             "Access to Floating Control "
-                                            "Status Register", FS);
+                                            "S""tatus Register", FS);
                                 }
                                 xc->setRegOtherThread(FLOATREG_FCSR + FP_Base_DepTag, data);
                             }});
@@ -776,7 +776,6 @@ decode OPCODE_HI default Unknown::unknown() {
                             bits(pageGrain, pageGrain.esp) == 1) {
                             SP = 1;
                         }
-                        IndexReg index = Index;
                         Ptr->insertAt(newEntry, Index & 0x7FFFFFFF, SP);
                     }});
                     0x06: tlbwr({{
@@ -842,7 +841,6 @@ decode OPCODE_HI default Unknown::unknown() {
                             bits(pageGrain, pageGrain.esp) == 1) {
                             SP = 1;
                         }
-                        IndexReg index = Index;
                         Ptr->insertAt(newEntry, Random, SP);
                     }});
 
diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa
index 1944d69d3..41f94e129 100644
--- a/src/arch/mips/isa/formats/mt.isa
+++ b/src/arch/mips/isa/formats/mt.isa
@@ -107,7 +107,7 @@ def template ThreadRegisterExecute {{
         Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
         {
             Fault fault = NoFault;
-            int64_t data;
+            int64_t data M5_VAR_USED;
             %(op_decl)s;
             %(op_rd)s;
 
@@ -126,17 +126,6 @@ def template ThreadRegisterExecute {{
                 } else if (vpeControl.targTC > mvpConf0.ptc) {
                     data = -1;
                 } else {
-                    int top_bit = 0;
-                    int bottom_bit = 0;
-
-                    if (MT_H == 1) {
-                        top_bit = 63;
-                        bottom_bit = 32;
-                    } else {
-                        top_bit = 31;
-                        bottom_bit = 0;
-                    }
-
                     %(code)s;
                 }
             } else {
@@ -203,10 +192,11 @@ def format MT_MFTR(code, *flags) {{
         flags += ('IsNonSpeculative', )
 #        code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
 
-        code += 'if (MT_H == 1) {\n'
-        code += 'data = bits(data, top_bit, bottom_bit);\n'
-        code += '}\n'
-        code += 'Rd = data;\n'
+        code += '''
+            if (MT_H)
+                data = bits(data, 63, 32);
+            Rd = data;
+        '''
 
         iop = InstObjParams(name, Name, 'MTOp', code, flags)
         header_output = BasicDeclare.subst(iop)
diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa
index c9f5da41d..4ce03b1c2 100644
--- a/src/arch/mips/isa/includes.isa
+++ b/src/arch/mips/isa/includes.isa
@@ -52,7 +52,9 @@ output decoder {{
 #include "arch/mips/faults.hh"
 #include "arch/mips/isa_traits.hh"
 #include "arch/mips/mt_constants.hh"
+#include "arch/mips/pagetable.hh"
 #include "arch/mips/pra_constants.hh"
+#include "arch/mips/tlb.hh"
 #include "arch/mips/utility.hh"
 #include "base/loader/symtab.hh"
 #include "base/cprintf.hh"
-- 
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