From 753adb38d5471d23315d1bcfc6a744d1c6e03975 Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Fri, 22 Jun 2007 19:03:42 -0400 Subject: mips import pt. 1 src/arch/mips/SConscript: "mips import pt.1". --HG-- extra : convert_revision : 2e393341938bebf32fb638a209262d074fad4cc1 --- src/arch/mips/isa/bitfields.isa | 21 +- src/arch/mips/isa/decoder.isa | 903 ++++++++++++++++++++++++++++++---- src/arch/mips/isa/formats/branch.isa | 54 +- src/arch/mips/isa/formats/control.isa | 127 +++-- src/arch/mips/isa/formats/dsp.isa | 218 ++++++++ src/arch/mips/isa/formats/formats.isa | 3 + src/arch/mips/isa/formats/fp.isa | 9 +- src/arch/mips/isa/formats/int.isa | 159 +++++- src/arch/mips/isa/formats/mem.isa | 117 +++-- src/arch/mips/isa/formats/mt.isa | 173 ++++++- src/arch/mips/isa/formats/tlbop.isa | 4 +- src/arch/mips/isa/formats/util.isa | 40 +- src/arch/mips/isa/includes.isa | 33 +- src/arch/mips/isa/operands.isa | 71 ++- 14 files changed, 1632 insertions(+), 300 deletions(-) create mode 100755 src/arch/mips/isa/formats/dsp.isa (limited to 'src/arch/mips/isa') diff --git a/src/arch/mips/isa/bitfields.isa b/src/arch/mips/isa/bitfields.isa index 35815bf1f..87be5ad13 100644 --- a/src/arch/mips/isa/bitfields.isa +++ b/src/arch/mips/isa/bitfields.isa @@ -28,6 +28,7 @@ // // Authors: Korey Sewell +//@TODO: Make sure the naming convention is consistent here. //////////////////////////////////////////////////////////////////// // // Bitfield definitions. @@ -58,6 +59,7 @@ def bitfield RT_RD <20:11>; def bitfield RD <15:11>; def bitfield INTIMM <15: 0>; +def bitfield RS_RT_INTIMM <25: 0>; // Floating-point operate format def bitfield FMT <25:21>; @@ -81,7 +83,7 @@ def bitfield BRANCH_CC <20:18>; // CP0 Register Select def bitfield SEL < 2: 0>; -// Interrupts +// INTERRUPTS def bitfield SC < 5: 5>; // Branch format @@ -100,3 +102,20 @@ def bitfield LSB <10: 6>; // M5 instructions def bitfield M5FUNC <7:0>; + +// DSP instructions +def bitfield OP <10:6>; +def bitfield OP_HI <10:9>; +def bitfield OP_LO <8:6>; +def bitfield DSPSA <23:21>; +def bitfield HILOSA <25:20>; +def bitfield RDDSPMASK <21:16>; +def bitfield WRDSPMASK <16:11>; +def bitfield ACSRC <22:21>; +def bitfield ACDST <12:11>; +def bitfield BP <12:11>; + +// MT Instructions +def bitfield POS <10: 6>; +def bitfield MT_U <5:5>; +def bitfield MT_H <4:4>; diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa index b5d1df4fc..0af84e36b 100644 --- a/src/arch/mips/isa/decoder.isa +++ b/src/arch/mips/isa/decoder.isa @@ -35,7 +35,7 @@ // The following instructions are specified in the MIPS32 ISA // Specification. Decoding closely follows the style specified // in the MIPS32 ISA specification document starting with Table -// A-2 (document available @ www.mips.com) +// A-2 (document available @ http://www.mips.com) // decode OPCODE_HI default Unknown::unknown() { //Table A-2 @@ -55,7 +55,7 @@ decode OPCODE_HI default Unknown::unknown() { //functions 0x0: decode RS { 0x0: decode RT_RD { - 0x0: decode SA default Nop::nop(){ + 0x0: decode SA default Nop::nop() { 0x1: WarnUnimpl::ssnop(); 0x3: WarnUnimpl::ehb(); } @@ -123,10 +123,9 @@ decode OPCODE_HI default Unknown::unknown() { } 0x1: decode HINT { - 0x1: jalr_hb({{ Rd = NNPC; NNPC = Rs; }}, IsCall, Link + 0x1: jalr_hb({{ Rd = NNPC; NNPC = Rs; }}, IsCall , ClearHazards); - default: jalr({{ Rd = NNPC; NNPC = Rs; }}, IsCall, - Link); + default: jalr({{ Rd = NNPC; NNPC = Rs; }}, IsCall); } } @@ -144,34 +143,29 @@ decode OPCODE_HI default Unknown::unknown() { } 0x2: decode FUNCTION_LO { - format HiLoMiscOp { - 0x0: mfhi({{ Rd = HI; }}); - 0x1: mthi({{ HI = Rs; }}); - 0x2: mflo({{ Rd = LO; }}); - 0x3: mtlo({{ LO = Rs; }}); - } + 0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }}); + 0x1: HiLoRdSelOp::mthi({{ HI_RD_SEL = Rs; }}); + 0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }}); + 0x3: HiLoRdSelOp::mtlo({{ LO_RD_SEL = Rs; }}); } 0x3: decode FUNCTION_LO { + format HiLoRdSelValOp { + 0x0: mult({{ val = Rs.sd * Rt.sd; }}); + 0x1: multu({{ val = Rs.ud * Rt.ud; }}); + } + format HiLoOp { - 0x0: mult({{ int64_t val = Rs.sd * Rt.sd; }}); - 0x1: multu({{ uint64_t val = Rs.ud * Rt.ud; }}); - 0x2: div({{ //Initialized to placate g++ - int64_t val = 0; - if (Rt.sd != 0) { - int64_t hi = Rs.sd % Rt.sd; - int64_t lo = Rs.sd / Rt.sd; - val = (hi << 32) | lo; - } - }}); - 0x3: divu({{ //Initialized to placate g++ - uint64_t val = 0; - if (Rt.ud != 0) { - uint64_t hi = Rs.ud % Rt.ud; - uint64_t lo = Rs.ud / Rt.ud; - val = (hi << 32) | lo; - } - }}); + 0x2: div({{ if (Rt.sd != 0) { + HI0 = Rs.sd % Rt.sd; + LO0 = Rs.sd / Rt.sd; + } + }}); + 0x3: divu({{ if (Rt.ud != 0) { + HI0 = Rs.ud % Rt.ud; + LO0 = Rs.ud / Rt.ud; + } + }}); } } @@ -245,6 +239,8 @@ decode OPCODE_HI default Unknown::unknown() { } 0x3: decode REGIMM_LO { + // from Table 5-4 MIPS32 REGIMM Encoding of rt Field (DSP ASE MANUAL) + 0x4: DspBranch::bposge32({{ cond = (dspctl<5:0> >= 32); }}); format WarnUnimpl { 0x7: synci(); } @@ -273,7 +269,15 @@ decode OPCODE_HI default Unknown::unknown() { 0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}}); 0x1: addiu({{ Rt.sw = Rs.sw + imm;}}); 0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }}); - 0x3: sltiu({{ Rt.uw = ( Rs.uw < (uint32_t)sextImm ) ? 1 : 0 }}); + + //Edited to include MIPS AVP Pass/Fail instructions and + //default to the sltiu instruction + 0x3: decode RS_RT_INTIMM { + 0xabc1: BasicOp::fail({{ exitSimLoop("AVP/SRVP Test Failed"); }}); + 0xabc2: BasicOp::pass({{ exitSimLoop("AVP/SRVP Test Passed"); }}); + default: sltiu({{ Rt.uw = ( Rs.uw < (uint32_t)sextImm ) ? 1 : 0 }}); + } + 0x4: andi({{ Rt.sw = Rs.sw & zextImm;}}); 0x5: ori({{ Rt.sw = Rs.sw | zextImm;}}); 0x6: xori({{ Rt.sw = Rs.sw ^ zextImm;}}); @@ -289,47 +293,296 @@ decode OPCODE_HI default Unknown::unknown() { 0x0: decode RS_MSB { 0x0: decode RS { format CP0Control { - 0x0: mfc0({{ Rt = xc->readMiscRegNoEffect(RD << 5 | SEL); }}); - 0x4: mtc0({{ xc->setMiscRegNoEffect(RD << 5 | SEL, Rt); }}); + 0x0: mfc0({{ Rt = CP0_RD_SEL; }}); + 0x4: mtc0({{ CP0_RD_SEL = Rt; }}); } - format MipsMT { - 0x8: mftr(); - 0xC: mttr(); - 0xB: decode RD { - 0x0: decode SC { - 0x0: dvpe(); - 0x1: evpe(); - } - 0x1: decode SC { - 0x0: dmt(); - 0x1: emt(); - 0xC: decode SC { - 0x0: di(); - 0x1: ei(); + + format MT_MFTR { // Decode MIPS MT MFTR instruction into sub-instructions + 0x8: decode MT_U { + 0x0: mftc0({{ data = xc->readRegOtherThread((RT << 3 | SEL) + + Ctrl_Base_DepTag); + }}); + 0x1: decode SEL { + 0x0: mftgpr({{ data = xc->readRegOtherThread(RT); }}); + 0x1: decode RT { + 0x0: mftlo_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPLo0); }}); + 0x1: mfthi_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPHi0); }}); + 0x2: mftacx_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPACX0); }}); + 0x4: mftlo_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPLo1); }}); + 0x5: mfthi_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPHi1); }}); + 0x6: mftacx_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPACX1); }}); + 0x8: mftlo_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPLo2); }}); + 0x9: mfthi_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPHi2); }}); + 0x10: mftacx_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPACX2); }}); + 0x12: mftlo_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPLo3); }}); + 0x13: mfthi_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPHi3); }}); + 0x14: mftacx_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPACX3); }}); + 0x16: mftdsp({{ data = xc->readRegOtherThread(MipsISA::DSPControl); }}); } + 0x2: decode MT_H { + 0x0: mftc1({{ data = xc->readRegOtherThread(RT + + FP_Base_DepTag); + }}); + 0x1: mfthc1({{ data = xc->readRegOtherThread(RT + + FP_Base_DepTag); + }}); + } + 0x3: cftc1({{ uint32_t fcsr_val = xc->readRegOtherThread(MipsISA::FCSR + + FP_Base_DepTag); + switch (RT) + { + case 0: + data = xc->readRegOtherThread(MipsISA::FIR + + Ctrl_Base_DepTag); + break; + case 25: + data = 0 | fcsr_val & 0xFE000000 >> 24 + | fcsr_val & 0x00800000 >> 23; + break; + case 26: + data = 0 | fcsr_val & 0x0003F07C; + break; + case 28: + data = 0 | fcsr_val & 0x00000F80 + | fcsr_val & 0x01000000 >> 21 + | fcsr_val & 0x00000003; + break; + case 31: + data = fcsr_val; + break; + default: + fatal("FP Control Value (%d) Not Valid"); + } + }}); } } } - format FailUnimpl { - 0xA: rdpgpr(); - 0xE: wrpgpr(); + format MT_MTTR { // Decode MIPS MT MTTR instruction into sub-instructions + 0xC: decode MT_U { + 0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Ctrl_Base_DepTag, + Rt); + }}); + 0x1: decode SEL { + 0x0: mttgpr({{ xc->setRegOtherThread(RD, Rt); }}); + 0x1: decode RT { + 0x0: mttlo_dsp0({{ xc->setRegOtherThread(MipsISA::DSPLo0, Rt); + }}); + 0x1: mtthi_dsp0({{ xc->setRegOtherThread(MipsISA::DSPHi0, + Rt); + }}); + 0x2: mttacx_dsp0({{ xc->setRegOtherThread(MipsISA::DSPACX0, + Rt); + }}); + 0x4: mttlo_dsp1({{ xc->setRegOtherThread(MipsISA::DSPLo1, + Rt); + }}); + 0x5: mtthi_dsp1({{ xc->setRegOtherThread(MipsISA::DSPHi1, + Rt); + }}); + 0x6: mttacx_dsp1({{ xc->setRegOtherThread(MipsISA::DSPACX1, + Rt); + }}); + 0x8: mttlo_dsp2({{ xc->setRegOtherThread(MipsISA::DSPLo2, + Rt); + }}); + 0x9: mtthi_dsp2({{ xc->setRegOtherThread(MipsISA::DSPHi2, + Rt); + }}); + 0x10: mttacx_dsp2({{ xc->setRegOtherThread(MipsISA::DSPACX2, + Rt); + }}); + 0x12: mttlo_dsp3({{ xc->setRegOtherThread(MipsISA::DSPLo3, + Rt); + }}); + 0x13: mtthi_dsp3({{ xc->setRegOtherThread(MipsISA::DSPHi3, + Rt); + }}); + 0x14: mttacx_dsp3({{ xc->setRegOtherThread(MipsISA::DSPACX3, Rt); + }}); + 0x16: mttdsp({{ xc->setRegOtherThread(MipsISA::DSPControl, Rt); }}); + } + 0x2: mttc1({{ uint64_t data = xc->readRegOtherThread(RD + + FP_Base_DepTag); + data = insertBits(data, top_bit, bottom_bit, Rt); + xc->setRegOtherThread(RD + FP_Base_DepTag, data); + }}); + 0x3: cttc1({{ uint32_t data; + switch (RD) + { + case 25: + data = 0 | (Rt.uw<7:1> << 25) // move 31...25 + | (FCSR & 0x01000000) // bit 24 + | (FCSR & 0x004FFFFF);// bit 22...0 + break; + + case 26: + data = 0 | (FCSR & 0xFFFC0000) // move 31...18 + | Rt.uw<17:12> << 12 // bit 17...12 + | (FCSR & 0x00000F80) << 7// bit 11...7 + | Rt.uw<6:2> << 2 // bit 6...2 + | (FCSR & 0x00000002); // bit 1...0 + break; + + case 28: + data = 0 | (FCSR & 0xFE000000) // move 31...25 + | Rt.uw<2:2> << 24 // bit 24 + | (FCSR & 0x00FFF000) << 23// bit 23...12 + | Rt.uw<11:7> << 7 // bit 24 + | (FCSR & 0x000007E) + | Rt.uw<1:0>;// bit 22...0 + break; + + case 31: + data = Rt.uw; + break; + + default: + panic("FP Control Value (%d) Not Available. Ignoring Access to" + "Floating Control Status Register", FS); + } + xc->setRegOtherThread(FCSR, data); + }}); + } + } + } + + + 0xB: decode RD { + format MT_Control { + 0x0: decode POS { + 0x0: decode SEL { + 0x1: decode SC { + 0x0: dvpe({{ Rt = MVPControl; + if (VPEConf0 == 1) { + MVPControl = insertBits(MVPControl, MVPC_EVP, 0); + } + }}); + 0x1: evpe({{ Rt = MVPControl; + if (VPEConf0 == 1) { + MVPControl = insertBits(MVPControl, MVPC_EVP, 1); + } + }}); + } + } + } + + 0x1: decode POS { + 0xF: decode SEL { + 0x1: decode SC { + 0x0: dmt({{ Rt = VPEControl; + VPEControl = insertBits(VPEControl, VPEC_TE, 0); + }}); + 0x1: emt({{ Rt = VPEControl; + VPEControl = insertBits(VPEControl, VPEC_TE, 1); + }}); + + } + } + } + } + 0xC: decode POS { + 0x0: decode SC { + 0x0: CP0Control::di({{ + if(Config_AR >= 1) // Rev 2.0 or beyond? + { + Rt = Status; + Status_IE = 0; + } + else // Enable this else branch once we actually set values for Config on init + { + fault = new ReservedInstructionFault(); + } + }}); + 0x1: CP0Control::ei({{ + if(Config_AR >= 1) + { + Rt = Status; + Status_IE = 1; + } + else + { + fault = new ReservedInstructionFault(); + } + }}); + } + } + } + + format CP0Control { + 0xA: rdpgpr({{ + if(Config_AR >= 1) + { // Rev 2 of the architecture + Rd = xc->tcBase()->readIntReg(Rt + NumIntRegs * SRSCtl_PSS); + } + else + { + fault = new ReservedInstructionFault(); + } + }}); + 0xE: wrpgpr({{ + if(Config_AR >= 1) + { // Rev 2 of the architecture + xc->tcBase()->setIntReg(Rd + NumIntRegs * SRSCtl_PSS,Rt); + } + else + { + fault = new ReservedInstructionFault(); + } + + }}); + } + } //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 0x1: decode FUNCTION { - format FailUnimpl { - 0x01: tlbr(); - 0x02: tlbwi(); - 0x06: tlbwr(); - 0x08: tlbp(); + format CP0Control { + 0x18: eret({{ + if(Status_ERL == 1){ + Status_ERL = 0; + NPC = ErrorEPC; + } + else{ + NPC = EPC; + Status_EXL = 0; + if(Config_AR >= 1 && SRSCtl_HSS > 0 && Status_BEV == 0){ + SRSCtl_CSS = SRSCtl_PSS; + } + } + // LLFlag = 0; + // ClearHazards(); ? + }}); + + 0x1F: deret({{ + // if(EJTagImplemented()) { + if(Debug_DM == 1){ + Debug_DM = 1; + Debug_IEXI = 0; + NPC = DEPC; + } + else + { + // Undefined; + } + //} // EJTag Implemented + //else { + // Reserved Instruction Exception + //} + }}); + } + + format FailUnimpl { + 0x01: tlbr(); // Need to hook up to TLB + 0x02: tlbwi(); // Need to hook up to TLB + 0x06: tlbwr();// Need to hook up to TLB + 0x08: tlbp();// Need to hook up to TLB - 0x18: eret(); - 0x1F: deret(); 0x20: wait(); } + } } @@ -949,45 +1202,37 @@ decode OPCODE_HI default Unknown::unknown() { 0x4: decode FUNCTION_HI { 0x0: decode FUNCTION_LO { 0x2: IntOp::mul({{ int64_t temp1 = Rs.sd * Rt.sd; - Rd.sw = temp1<31:0> + Rd.sw = temp1<31:0>; }}); - format HiLoOp { - 0x0: madd({{ int64_t val = ((int64_t) HI << 32 | LO) + - (Rs.sd * Rt.sd); - }}); - 0x1: maddu({{ uint64_t val = ((uint64_t) HI << 32 | LO) + - (Rs.ud * Rt.ud); - }}); - 0x4: msub({{ int64_t val = ((int64_t) HI << 32 | LO) - - (Rs.sd * Rt.sd); - }}); - 0x5: msubu({{ uint64_t val = ((uint64_t) HI << 32 | LO) - - (Rs.ud * Rt.ud); - }}); + format HiLoRdSelValOp { + 0x0: madd({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.sd * Rt.sd); }}); + 0x1: maddu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.ud * Rt.ud); }}); + 0x4: msub({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.sd * Rt.sd); }}); + 0x5: msubu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.ud * Rt.ud); }}); } } 0x4: decode FUNCTION_LO { format BasicOp { 0x0: clz({{ int cnt = 32; - for (int idx = 31; idx >= 0; idx--) { - if( Rs == 1) { - cnt = 31 - idx; - break; - } - } - Rd.uw = cnt; - }}); + for (int idx = 31; idx >= 0; idx--) { + if( Rs == 1) { + cnt = 31 - idx; + break; + } + } + Rd.uw = cnt; + }}); 0x1: clo({{ int cnt = 32; - for (int idx = 31; idx >= 0; idx--) { - if( Rs == 0) { - cnt = 31 - idx; - break; - } - } - Rd.uw = cnt; - }}); + for (int idx = 31; idx >= 0; idx--) { + if( Rs == 0) { + cnt = 31 - idx; + break; + } + } + Rd.uw = cnt; + }}); } } @@ -1010,9 +1255,337 @@ decode OPCODE_HI default Unknown::unknown() { } 0x1: decode FUNCTION_LO { - format MipsMT { - 0x0: fork(); - 0x1: yield(); + format MT_Control { + 0x0: fork({{ forkThread(xc->tcBase(), fault, RD, Rs, Rt); }}, + UserMode); + 0x1: yield({{ Rd.sw = yieldThread(xc->tcBase(), fault, Rs.sw, YQMask); }}, + UserMode); + } + + //Table 5-9 MIPS32 LX Encoding of the op Field (DSP ASE MANUAL) + 0x2: decode OP_HI { + 0x0: decode OP_LO { + format LoadIndexedMemory { + 0x0: lwx({{ Rd.sw = Mem.sw; }}); + 0x4: lhx({{ Rd.sw = Mem.sh; }}); + 0x6: lbux({{ Rd.uw = Mem.ub; }}); + } + } + } + 0x4: DspIntOp::insv({{ int pos = dspctl<5:0>; + int size = dspctl<12:7>-1; + Rt.uw = insertBits( Rt.uw, pos+size, pos, Rs.uw ); }}); + } + + 0x2: decode FUNCTION_LO { + + //Table 5-5 MIPS32 ADDU.QB Encoding of the op Field (DSP ASE MANUAL) + 0x0: decode OP_HI { + 0x0: decode OP_LO { + format DspIntOp { + 0x0: addu_qb({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_QB, + NOSATURATE, UNSIGNED, &dspctl ); }}); + 0x1: subu_qb({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_QB, + NOSATURATE, UNSIGNED, &dspctl ); }}); + 0x4: addu_s_qb({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_QB, + SATURATE, UNSIGNED, &dspctl ); }}); + 0x5: subu_s_qb({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_QB, + SATURATE, UNSIGNED, &dspctl ); }}); + 0x6: muleu_s_ph_qbl({{ Rd.uw = dspMuleu( Rs.uw, Rt.uw, + MODE_L, &dspctl ); }}); + 0x7: muleu_s_ph_qbr({{ Rd.uw = dspMuleu( Rs.uw, Rt.uw, + MODE_R, &dspctl ); }}); + } + } + 0x1: decode OP_LO { + format DspIntOp { + 0x0: addu_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH, + NOSATURATE, UNSIGNED, &dspctl ); }}); + 0x1: subu_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH, + NOSATURATE, UNSIGNED, &dspctl ); }}); + 0x2: addq_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH, + NOSATURATE, SIGNED, &dspctl ); }}); + 0x3: subq_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH, + NOSATURATE, SIGNED, &dspctl ); }}); + 0x4: addu_s_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH, + SATURATE, UNSIGNED, &dspctl ); }}); + 0x5: subu_s_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH, + SATURATE, UNSIGNED, &dspctl ); }}); + 0x6: addq_s_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH, + SATURATE, SIGNED, &dspctl ); }}); + 0x7: subq_s_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH, + SATURATE, SIGNED, &dspctl ); }}); + } + } + 0x2: decode OP_LO { + format DspIntOp { + 0x0: addsc({{ int64_t dresult; + dresult = Rs.ud + Rt.ud; + Rd.sw = dresult<31:0>; + dspctl = insertBits( dspctl, 13, 13, + dresult<32:32> ); }}); + 0x1: addwc({{ int64_t dresult; + dresult = Rs.sd + Rt.sd + dspctl<13:13>; + Rd.sw = dresult<31:0>; + if( dresult<32:32> != dresult<31:31> ) + dspctl = insertBits( dspctl, 20, 20, 1 ); }}); + 0x2: modsub({{ Rd.sw = (Rs.sw == 0) ? Rt.sw<23:8> : Rs.sw - Rt.sw<7:0>; }}); + 0x4: raddu_w_qb({{ Rd.uw = Rs.uw<31:24> + Rs.uw<23:16> + + Rs.uw<15:8> + Rs.uw<7:0>; }}); + 0x6: addq_s_w({{ Rd.sw = dspAdd( Rs.sw, Rt.sw, SIMD_FMT_W, + SATURATE, SIGNED, &dspctl ); }}); + 0x7: subq_s_w({{ Rd.sw = dspSub( Rs.sw, Rt.sw, SIMD_FMT_W, + SATURATE, SIGNED, &dspctl ); }}); + } + } + 0x3: decode OP_LO { + format DspIntOp { + 0x4: muleq_s_w_phl({{ Rd.sw = dspMuleq( Rs.sw, Rt.sw, + MODE_L, &dspctl ); }}); + 0x5: muleq_s_w_phr({{ Rd.sw = dspMuleq( Rs.sw, Rt.sw, + MODE_R, &dspctl ); }}); + 0x6: mulq_s_ph({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_PH, + SATURATE, NOROUND, &dspctl ); }}); + 0x7: mulq_rs_ph({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_PH, + SATURATE, ROUND, &dspctl ); }}); + } + } + } + + //Table 5-6 MIPS32 CMPU_EQ_QB Encoding of the op Field (DSP ASE MANUAL) + 0x1: decode OP_HI { + 0x0: decode OP_LO { + format DspIntOp { + 0x0: cmpu_eq_qb({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_QB, + UNSIGNED, CMP_EQ, &dspctl ); }}); + 0x1: cmpu_lt_qb({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_QB, + UNSIGNED, CMP_LT, &dspctl ); }}); + 0x2: cmpu_le_qb({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_QB, + UNSIGNED, CMP_LE, &dspctl ); }}); + 0x3: pick_qb({{ Rd.uw = dspPick( Rs.uw, Rt.uw, + SIMD_FMT_QB, &dspctl ); }}); + 0x4: cmpgu_eq_qb({{ Rd.uw = dspCmpg( Rs.uw, Rt.uw, SIMD_FMT_QB, + UNSIGNED, CMP_EQ ); }}); + 0x5: cmpgu_lt_qb({{ Rd.uw = dspCmpg( Rs.uw, Rt.uw, SIMD_FMT_QB, + UNSIGNED, CMP_LT ); }}); + 0x6: cmpgu_le_qb({{ Rd.uw = dspCmpg( Rs.uw, Rt.uw, SIMD_FMT_QB, + UNSIGNED, CMP_LE ); }}); + } + } + 0x1: decode OP_LO { + format DspIntOp { + 0x0: cmp_eq_ph({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_PH, + SIGNED, CMP_EQ, &dspctl ); }}); + 0x1: cmp_lt_ph({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_PH, + SIGNED, CMP_LT, &dspctl ); }}); + 0x2: cmp_le_ph({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_PH, + SIGNED, CMP_LE, &dspctl ); }}); + 0x3: pick_ph({{ Rd.uw = dspPick( Rs.uw, Rt.uw, + SIMD_FMT_PH, &dspctl ); }}); + 0x4: precrq_qb_ph({{ Rd.uw = Rs.uw<31:24> << 24 | + Rs.uw<15:8> << 16 | + Rt.uw<31:24> << 8 | + Rt.uw<15:8>; }}); + 0x5: precr_qb_ph({{ Rd.uw = Rs.uw<23:16> << 24 | + Rs.uw<7:0> << 16 | + Rt.uw<23:16> << 8 | + Rt.uw<7:0>; }}); + 0x6: packrl_ph({{ Rd.uw = dspPack( Rs.uw, Rt.uw, + SIMD_FMT_PH ); }}); + 0x7: precrqu_s_qb_ph({{ Rd.uw = dspPrecrqu( Rs.uw, Rt.uw, &dspctl ); }}); + } + } + 0x2: decode OP_LO { + format DspIntOp { + 0x4: precrq_ph_w({{ Rd.uw = Rs.uw<31:16> << 16 | Rt.uw<31:16>; }}); + 0x5: precrq_rs_ph_w({{ Rd.uw = dspPrecrq( Rs.uw, Rt.uw, SIMD_FMT_W, &dspctl ); }}); + } + } + 0x3: decode OP_LO { + format DspIntOp { + 0x0: cmpgdu_eq_qb({{ Rd.uw = dspCmpgd( Rs.uw, Rt.uw, SIMD_FMT_QB, + UNSIGNED, CMP_EQ, &dspctl ); }}); + 0x1: cmpgdu_lt_qb({{ Rd.uw = dspCmpgd( Rs.uw, Rt.uw, SIMD_FMT_QB, + UNSIGNED, CMP_LT, &dspctl ); }}); + 0x2: cmpgdu_le_qb({{ Rd.uw = dspCmpgd( Rs.uw, Rt.uw, SIMD_FMT_QB, + UNSIGNED, CMP_LE, &dspctl ); }}); + 0x6: precr_sra_ph_w({{ Rt.uw = dspPrecrSra( Rt.uw, Rs.uw, RD, + SIMD_FMT_W, NOROUND ); }}); + 0x7: precr_sra_r_ph_w({{ Rt.uw = dspPrecrSra( Rt.uw, Rs.uw, RD, + SIMD_FMT_W, ROUND ); }}); + } + } + } + + //Table 5-7 MIPS32 ABSQ_S.PH Encoding of the op Field (DSP ASE MANUAL) + 0x2: decode OP_HI { + 0x0: decode OP_LO { + format DspIntOp { + 0x1: absq_s_qb({{ Rd.sw = dspAbs( Rt.sw, SIMD_FMT_QB, &dspctl );}}); + 0x2: repl_qb({{ Rd.uw = RS_RT<7:0> << 24 | + RS_RT<7:0> << 16 | + RS_RT<7:0> << 8 | + RS_RT<7:0>; }}); + 0x3: replv_qb({{ Rd.sw = Rt.uw<7:0> << 24 | + Rt.uw<7:0> << 16 | + Rt.uw<7:0> << 8 | + Rt.uw<7:0>; }}); + 0x4: precequ_ph_qbl({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, + SIMD_FMT_PH, SIGNED, MODE_L ); }}); + 0x5: precequ_ph_qbr({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, + SIMD_FMT_PH, SIGNED, MODE_R ); }}); + 0x6: precequ_ph_qbla({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, + SIMD_FMT_PH, SIGNED, MODE_LA ); }}); + 0x7: precequ_ph_qbra({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, + SIMD_FMT_PH, SIGNED, MODE_RA ); }}); + } + } + 0x1: decode OP_LO { + format DspIntOp { + 0x1: absq_s_ph({{ Rd.sw = dspAbs( Rt.sw, SIMD_FMT_PH, &dspctl ); }}); + 0x2: repl_ph({{ Rd.uw = (sext<10>(RS_RT))<15:0> << 16 | + (sext<10>(RS_RT))<15:0>; }}); + 0x3: replv_ph({{ Rd.uw = Rt.uw<15:0> << 16 | + Rt.uw<15:0>; }}); + 0x4: preceq_w_phl({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_PH, SIGNED, + SIMD_FMT_W, SIGNED, MODE_L ); }}); + 0x5: preceq_w_phr({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_PH, SIGNED, + SIMD_FMT_W, SIGNED, MODE_R ); }}); + } + } + 0x2: decode OP_LO { + format DspIntOp { + 0x1: absq_s_w({{ Rd.sw = dspAbs( Rt.sw, SIMD_FMT_W, &dspctl ); }}); + } + } + 0x3: decode OP_LO { + 0x3: IntOp::bitrev({{ Rd.uw = bitrev( Rt.uw<15:0> ); }}); + format DspIntOp { + 0x4: preceu_ph_qbl({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, + SIMD_FMT_PH, UNSIGNED, MODE_L ); }}); + 0x5: preceu_ph_qbr({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, + SIMD_FMT_PH, UNSIGNED, MODE_R ); }}); + 0x6: preceu_ph_qbla({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, + SIMD_FMT_PH, UNSIGNED, MODE_LA ); }}); + 0x7: preceu_ph_qbra({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, + SIMD_FMT_PH, UNSIGNED, MODE_RA ); }}); + } + } + } + + //Table 5-8 MIPS32 SHLL.QB Encoding of the op Field (DSP ASE MANUAL) + 0x3: decode OP_HI { + 0x0: decode OP_LO { + format DspIntOp { + 0x0: shll_qb({{ Rd.sw = dspShll( Rt.sw, RS, SIMD_FMT_QB, + NOSATURATE, UNSIGNED, &dspctl ); }}); + 0x1: shrl_qb({{ Rd.sw = dspShrl( Rt.sw, RS, SIMD_FMT_QB, + UNSIGNED ); }}); + 0x2: shllv_qb({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_QB, + NOSATURATE, UNSIGNED, &dspctl ); }}); + 0x3: shrlv_qb({{ Rd.sw = dspShrl( Rt.sw, Rs.sw, SIMD_FMT_QB, + UNSIGNED ); }}); + 0x4: shra_qb({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_QB, + NOROUND, SIGNED, &dspctl ); }}); + 0x5: shra_r_qb({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_QB, + ROUND, SIGNED, &dspctl ); }}); + 0x6: shrav_qb({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_QB, + NOROUND, SIGNED, &dspctl ); }}); + 0x7: shrav_r_qb({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_QB, + ROUND, SIGNED, &dspctl ); }}); + } + } + 0x1: decode OP_LO { + format DspIntOp { + 0x0: shll_ph({{ Rd.uw = dspShll( Rt.uw, RS, SIMD_FMT_PH, + NOSATURATE, SIGNED, &dspctl ); }}); + 0x1: shra_ph({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_PH, + NOROUND, SIGNED, &dspctl ); }}); + 0x2: shllv_ph({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_PH, + NOSATURATE, SIGNED, &dspctl ); }}); + 0x3: shrav_ph({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_PH, + NOROUND, SIGNED, &dspctl ); }}); + 0x4: shll_s_ph({{ Rd.sw = dspShll( Rt.sw, RS, SIMD_FMT_PH, + SATURATE, SIGNED, &dspctl ); }}); + 0x5: shra_r_ph({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_PH, + ROUND, SIGNED, &dspctl ); }}); + 0x6: shllv_s_ph({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_PH, + SATURATE, SIGNED, &dspctl ); }}); + 0x7: shrav_r_ph({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_PH, + ROUND, SIGNED, &dspctl ); }}); + } + } + 0x2: decode OP_LO { + format DspIntOp { + 0x4: shll_s_w({{ Rd.sw = dspShll( Rt.sw, RS, SIMD_FMT_W, + SATURATE, SIGNED, &dspctl ); }}); + 0x5: shra_r_w({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_W, + ROUND, SIGNED, &dspctl ); }}); + 0x6: shllv_s_w({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_W, + SATURATE, SIGNED, &dspctl ); }}); + 0x7: shrav_r_w({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_W, + ROUND, SIGNED, &dspctl ); }}); + } + } + 0x3: decode OP_LO { + format DspIntOp { + 0x1: shrl_ph({{ Rd.sw = dspShrl( Rt.sw, RS, SIMD_FMT_PH, + UNSIGNED ); }}); + 0x3: shrlv_ph({{ Rd.sw = dspShrl( Rt.sw, Rs.sw, SIMD_FMT_PH, + UNSIGNED ); }}); + } + } + } + } + + 0x3: decode FUNCTION_LO { + + //Table 3.12 MIPS32 ADDUH.QB Encoding of the op Field (DSP ASE Rev2 Manual) + 0x0: decode OP_HI { + 0x0: decode OP_LO { + format DspIntOp { + 0x0: adduh_qb({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_QB, + NOROUND, UNSIGNED ); }}); + 0x1: subuh_qb({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_QB, + NOROUND, UNSIGNED ); }}); + 0x2: adduh_r_qb({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_QB, + ROUND, UNSIGNED ); }}); + 0x3: subuh_r_qb({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_QB, + ROUND, UNSIGNED ); }}); + } + } + 0x1: decode OP_LO { + format DspIntOp { + 0x0: addqh_ph({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_PH, + NOROUND, SIGNED ); }}); + 0x1: subqh_ph({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_PH, + NOROUND, SIGNED ); }}); + 0x2: addqh_r_ph({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_PH, + ROUND, SIGNED ); }}); + 0x3: subqh_r_ph({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_PH, + ROUND, SIGNED ); }}); + 0x4: mul_ph({{ Rd.sw = dspMul( Rs.sw, Rt.sw, SIMD_FMT_PH, + NOSATURATE, &dspctl ); }}); + 0x6: mul_s_ph({{ Rd.sw = dspMul( Rs.sw, Rt.sw, SIMD_FMT_PH, + SATURATE, &dspctl ); }}); + } + } + 0x2: decode OP_LO { + format DspIntOp { + 0x0: addqh_w({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_W, + NOROUND, SIGNED ); }}); + 0x1: subqh_w({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_W, + NOROUND, SIGNED ); }}); + 0x2: addqh_r_w({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_W, + ROUND, SIGNED ); }}); + 0x3: subqh_r_w({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_W, + ROUND, SIGNED ); }}); + 0x6: mulq_s_w({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_W, + SATURATE, NOROUND, &dspctl ); }}); + 0x7: mulq_rs_w({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_W, + SATURATE, ROUND, &dspctl ); }}); + } + } } } @@ -1020,9 +1593,9 @@ decode OPCODE_HI default Unknown::unknown() { 0x4: decode SA { format BasicOp { 0x02: wsbh({{ Rd.uw = Rt.uw<23:16> << 24 | - Rt.uw<31:24> << 16 | - Rt.uw<7:0> << 8 | - Rt.uw<15:8>; + Rt.uw<31:24> << 16 | + Rt.uw<7:0> << 8 | + Rt.uw<15:8>; }}); 0x10: seb({{ Rd.sw = Rt.sb; }}); 0x18: seh({{ Rd.sw = Rt.sh; }}); @@ -1030,8 +1603,145 @@ decode OPCODE_HI default Unknown::unknown() { } 0x6: decode FUNCTION_LO { + + //Table 5-10 MIPS32 DPAQ.W.PH Encoding of the op Field (DSP ASE MANUAL) + 0x0: decode OP_HI { + 0x0: decode OP_LO { + format DspHiLoOp { + 0x0: dpa_w_ph({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST, + SIMD_FMT_PH, SIGNED, MODE_L ); }}); + 0x1: dps_w_ph({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST, + SIMD_FMT_PH, SIGNED, MODE_L ); }}); + 0x2: mulsa_w_ph({{ dspac = dspMulsa( dspac, Rs.sw, Rt.sw, + ACDST, SIMD_FMT_PH ); }}); + 0x3: dpau_h_qbl({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST, + SIMD_FMT_QB, UNSIGNED, MODE_L ); }}); + 0x4: dpaq_s_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, + SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }}); + 0x5: dpsq_s_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, + SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }}); + 0x6: mulsaq_s_w_ph({{ dspac = dspMulsaq( dspac, Rs.sw, Rt.sw, + ACDST, SIMD_FMT_PH, &dspctl ); }}); + 0x7: dpau_h_qbr({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST, + SIMD_FMT_QB, UNSIGNED, MODE_R ); }}); + } + } + 0x1: decode OP_LO { + format DspHiLoOp { + 0x0: dpax_w_ph({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST, + SIMD_FMT_PH, SIGNED, MODE_X ); }}); + 0x1: dpsx_w_ph({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST, + SIMD_FMT_PH, SIGNED, MODE_X ); }}); + 0x3: dpsu_h_qbl({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST, + SIMD_FMT_QB, UNSIGNED, MODE_L ); }}); + 0x4: dpaq_sa_l_w({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_W, + SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }}); + 0x5: dpsq_sa_l_w({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_W, + SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }}); + 0x7: dpsu_h_qbr({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST, + SIMD_FMT_QB, UNSIGNED, MODE_R ); }}); + } + } + 0x2: decode OP_LO { + format DspHiLoOp { + 0x0: maq_sa_w_phl({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH, + MODE_L, SATURATE, &dspctl ); }}); + 0x2: maq_sa_w_phr({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH, + MODE_R, SATURATE, &dspctl ); }}); + 0x4: maq_s_w_phl({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH, + MODE_L, NOSATURATE, &dspctl ); }}); + 0x6: maq_s_w_phr({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH, + MODE_R, NOSATURATE, &dspctl ); }}); + } + } + 0x3: decode OP_LO { + format DspHiLoOp { + 0x0: dpaqx_s_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, + SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }}); + 0x1: dpsqx_s_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, + SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }}); + 0x2: dpaqx_sa_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, + SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }}); + 0x3: dpsqx_sa_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, + SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }}); + } + } + } + + //Table 3.3 MIPS32 APPEND Encoding of the op Field + 0x1: decode OP_HI { + 0x0: decode OP_LO { + format IntOp { + 0x0: append({{ Rt.uw = (Rt.uw << RD) | bits(Rs.uw,RD-1,0); }}); + 0x1: prepend({{ Rt.uw = (Rt.uw >> RD) | (bits(Rs.uw,RD-1,0) << 32-RD); }}); + } + } + 0x2: decode OP_LO { + format IntOp { + 0x0: balign({{ Rt.uw = (Rt.uw << (8*BP)) | (Rs.uw >> (8*(4-BP))); }}); + } + } + } + 0x7: FailUnimpl::rdhwr(); } + + 0x7: decode FUNCTION_LO { + + //Table 5-11 MIPS32 EXTR.W Encoding of the op Field (DSP ASE MANUAL) + 0x0: decode OP_HI { + 0x0: decode OP_LO { + format DspHiLoOp { + 0x0: extr_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS, + NOROUND, NOSATURATE, &dspctl ); }}); + 0x1: extrv_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, Rs.uw, + NOROUND, NOSATURATE, &dspctl ); }}); + 0x2: extp({{ Rt.uw = dspExtp( dspac, RS, &dspctl ); }}); + 0x3: extpv({{ Rt.uw = dspExtp( dspac, Rs.uw, &dspctl ); }}); + 0x4: extr_r_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS, + ROUND, NOSATURATE, &dspctl ); }}); + 0x5: extrv_r_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, Rs.uw, + ROUND, NOSATURATE, &dspctl ); }}); + 0x6: extr_rs_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS, + ROUND, SATURATE, &dspctl ); }}); + 0x7: extrv_rs_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, Rs.uw, + ROUND, SATURATE, &dspctl ); }}); + } + } + 0x1: decode OP_LO { + format DspHiLoOp { + 0x2: extpdp({{ Rt.uw = dspExtpd( dspac, RS, &dspctl ); }}); + 0x3: extpdpv({{ Rt.uw = dspExtpd( dspac, Rs.uw, &dspctl ); }}); + 0x6: extr_s_h({{ Rt.uw = dspExtr( dspac, SIMD_FMT_PH, RS, + NOROUND, SATURATE, &dspctl ); }}); + 0x7: extrv_s_h({{ Rt.uw = dspExtr( dspac, SIMD_FMT_PH, Rs.uw, + NOROUND, SATURATE, &dspctl ); }}); + } + } + 0x2: decode OP_LO { + format DspIntOp { + 0x2: rddsp({{ Rd.uw = readDSPControl( &dspctl, RDDSPMASK ); }}); + 0x3: wrdsp({{ writeDSPControl( &dspctl, Rs.uw, WRDSPMASK ); }}); + } + } + 0x3: decode OP_LO { + format DspHiLoOp { + 0x2: shilo({{ if( sext<6>(HILOSA) < 0 ) + dspac = (uint64_t)dspac << -sext<6>(HILOSA); + else + dspac = (uint64_t)dspac >> sext<6>(HILOSA); }}); + 0x3: shilov({{ if( sext<6>(Rs.sw<5:0>) < 0 ) + dspac = (uint64_t)dspac << -sext<6>(Rs.sw<5:0>); + else + dspac = (uint64_t)dspac >> sext<6>(Rs.sw<5:0>); }}); + 0x7: mthlip({{ dspac = dspac << 32; + dspac |= Rs.uw; + dspctl = insertBits( dspctl, 5, 0, + dspctl<5:0>+32 ); }}); + } + } + } + } } } @@ -1047,13 +1757,13 @@ decode OPCODE_HI default Unknown::unknown() { format LoadUnalignedMemory { 0x2: lwl({{ uint32_t mem_shift = 24 - (8 * byte_offset); Rt.uw = mem_word << mem_shift | - Rt.uw & mask(mem_shift); + Rt.uw & mask(mem_shift); }}); 0x6: lwr({{ uint32_t mem_shift = 8 * byte_offset; Rt.uw = Rt.uw & (mask(mem_shift) << (32 - mem_shift)) | - mem_word >> mem_shift; + mem_word >> mem_shift; }}); - } + } } 0x5: decode OPCODE_LO { @@ -1093,9 +1803,6 @@ decode OPCODE_HI default Unknown::unknown() { 0x0: StoreCond::sc({{ Mem.uw = Rt.uw;}}, {{ uint64_t tmp = write_result; Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw; - if (tmp == 1) { - xc->setStCondFailures(0); - } }}, mem_flags=LOCKED, inst_flags = IsStoreConditional); format StoreMemory { diff --git a/src/arch/mips/isa/formats/branch.isa b/src/arch/mips/isa/formats/branch.isa index a67f04dca..e959e4c1b 100644 --- a/src/arch/mips/isa/formats/branch.isa +++ b/src/arch/mips/isa/formats/branch.isa @@ -36,6 +36,7 @@ output header {{ #include + using namespace std; /** * Base class for instructions whose disassembly is not purely a @@ -216,7 +217,7 @@ output decoder {{ } }}; -def format Branch(code,*opt_flags) {{ +def format Branch(code, *opt_flags) {{ not_taken_code = ' NNPC = NNPC;\n' not_taken_code += '} \n' @@ -230,13 +231,13 @@ def format Branch(code,*opt_flags) {{ not_taken_code = ' NPC = NNPC;\n' not_taken_code += ' NNPC = NNPC + 4;\n' not_taken_code += '} \n' - inst_flags = ('IsCondDelaySlot', ) + inst_flags += ('IsCondDelaySlot', ) else: inst_flags += (x, ) #Take into account uncond. branch instruction - if 'cond == 1' in code: - inst_flags += ('IsUnCondControl', ) + if 'cond = 1' in code: + inst_flags += ('IsUncondControl', ) else: inst_flags += ('IsCondControl', ) @@ -254,6 +255,51 @@ def format Branch(code,*opt_flags) {{ exec_output = BasicExecute.subst(iop) }}; +def format DspBranch(code, *opt_flags) {{ + not_taken_code = ' NNPC = NNPC;\n' + not_taken_code += '} \n' + + #Build Instruction Flags + #Use Link & Likely Flags to Add Link/Condition Code + inst_flags = ('IsDirectControl', ) + for x in opt_flags: + if x == 'Link': + code += 'R31 = NNPC;\n' + elif x == 'Likely': + not_taken_code = ' NPC = NNPC;\n' + not_taken_code += ' NNPC = NNPC + 4;\n' + not_taken_code += '} \n' + inst_flags += ('IsCondDelaySlot', ) + else: + inst_flags += (x, ) + + #Take into account uncond. branch instruction + if 'cond = 1' in code: + inst_flags += ('IsUncondControl', ) + else: + inst_flags += ('IsCondControl', ) + + #Declaration code + decl_code = 'bool cond;\n' + decl_code += 'uint32_t dspctl;\n' + + #Fetch code + fetch_code = 'dspctl = DSPControl;\n' + + #Condition code + code = decl_code + fetch_code + code + code += 'if (cond) {\n' + code += ' NNPC = NPC + disp;\n' + code += '} else {\n' + code += not_taken_code + + iop = InstObjParams(name, Name, 'Branch', code, inst_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = BasicExecute.subst(iop) +}}; + def format Jump(code, *opt_flags) {{ #Build Instruction Flags #Use Link Flag to Add Link Code diff --git a/src/arch/mips/isa/formats/control.isa b/src/arch/mips/isa/formats/control.isa index 1c63a6e22..1de2948be 100644 --- a/src/arch/mips/isa/formats/control.isa +++ b/src/arch/mips/isa/formats/control.isa @@ -30,45 +30,32 @@ //////////////////////////////////////////////////////////////////// // -// Integer operate instructions +// Coprocessor instructions // //Outputs to decoder.hh output header {{ - class Control : public MipsStaticInst - { - protected: - - /// Constructor - Control(const char *mnem, MachInst _machInst, OpClass __opClass) : - MipsStaticInst(mnem, _machInst, __opClass) - { - } - - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; - - class CP0Control : public Control + class CP0Control : public MipsStaticInst { protected: /// Constructor CP0Control(const char *mnem, MachInst _machInst, OpClass __opClass) : - Control(mnem, _machInst, __opClass) + MipsStaticInst(mnem, _machInst, __opClass) { } std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; - class CP1Control : public Control + class CP1Control : public MipsStaticInst { protected: /// Constructor CP1Control(const char *mnem, MachInst _machInst, OpClass __opClass) : - Control(mnem, _machInst, __opClass) + MipsStaticInst(mnem, _machInst, __opClass) { } @@ -77,46 +64,34 @@ output header {{ }}; -//Outputs to decoder.cc -output decoder {{ - std::string Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const +// Basic instruction class execute method template. +def template ControlExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { - std::stringstream ss; - - ccprintf(ss, "%-10s ", mnemonic); - - if (mnemonic == "mfc0" || mnemonic == "mtc0") { - ccprintf(ss, "%-10s %d,%d,%d", mnemonic,RT,RD,SEL); - } else { - - // just print the first dest... if there's a second one, - // it's generally implicit - if (_numDestRegs > 0) { - printReg(ss, _destRegIdx[0]); - } - - ss << ", "; - - // just print the first two source regs... if there's - // a third one, it's a read-modify-write dest (Rc), - // e.g. for CMOVxx - if (_numSrcRegs > 0) { - printReg(ss, _srcRegIdx[0]); + Fault fault = NoFault; + %(op_decl)s; + %(op_rd)s; + + if (isCoprocessorEnabled(xc, 0)) { + %(code)s; + } else { + fault = new CoprocessorUnusableFault(); } - if (_numSrcRegs > 1) { - ss << ", "; - printReg(ss, _srcRegIdx[1]); + if(fault == NoFault) + { + %(op_wb)s; } - } - - return ss.str(); + return fault; } +}}; +//Outputs to decoder.cc +output decoder {{ std::string CP0Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; - ccprintf(ss, "%-10s r%d, r%d, %d", mnemonic, RT, RD, SEL); + ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL); return ss.str(); } @@ -129,28 +104,50 @@ output decoder {{ }}; -def format System(code, *flags) {{ - iop = InstObjParams(name, Name, 'Control', code, flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecode.subst(iop) - exec_output = BasicExecute.subst(iop) +output exec {{ + bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num) + { + switch(cop_num) + { + case 0: +#if FULL_SYSTEM + if((xc->readMiscReg(MipsISA::Status) & 0x10000006) == 0 && (xc->readMiscReg(MipsISA::Debug) & 0x40000000 ) == 0) { + // Unable to use Status_CU0, etc directly, using bitfields & masks + return false; + } +#else + //printf("Syscall Emulation Mode: CP0 Enable Check defaults to TRUE\n"); +#endif + break; + case 1: + break; + case 2: + break; + case 3: + break; + default: panic("Invalid Coprocessor Number Specified"); + break; + } + return true; + } }}; def format CP0Control(code, *flags) {{ - iop = InstObjParams(name, Name, 'CP0Control', code, flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecode.subst(iop) - exec_output = BasicExecute.subst(iop) + flags += ('IsNonSpeculative', ) + iop = InstObjParams(name, Name, 'CP0Control', code, flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = ControlExecute.subst(iop) }}; def format CP1Control(code, *flags) {{ - iop = InstObjParams(name, Name, 'CP1Control', code, flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecode.subst(iop) - exec_output = BasicExecute.subst(iop) + flags += ('IsNonSpeculative', ) + iop = InstObjParams(name, Name, 'CP1Control', code, flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = ControlExecute.subst(iop) }}; diff --git a/src/arch/mips/isa/formats/dsp.isa b/src/arch/mips/isa/formats/dsp.isa new file mode 100755 index 000000000..768f3dd7d --- /dev/null +++ b/src/arch/mips/isa/formats/dsp.isa @@ -0,0 +1,218 @@ +// -*- mode:c++ -*- + +// Copyright (c) 2006 The Regents of The University of Michigan +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer; +// redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution; +// neither the name of the copyright holders nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Authors: Korey Sewell + +//////////////////////////////////////////////////////////////////// +// +// DSP integer operate instructions +// +output header {{ +#include + using namespace std; + /** + * Base class for integer operations. + */ + class DspIntOp : public MipsStaticInst + { + protected: + + /// Constructor + DspIntOp(const char *mnem, MachInst _machInst, OpClass __opClass) : + MipsStaticInst(mnem, _machInst, __opClass) + { + } + }; + + class DspHiLoOp : public MipsStaticInst + { + protected: + + /// Constructor + DspHiLoOp(const char *mnem, MachInst _machInst, OpClass __opClass) : + MipsStaticInst(mnem, _machInst, __opClass) + { + } + }; +}}; + +// Dsp instruction class execute method template. +def template DspExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + Fault fault = NoFault; + + %(op_decl)s; + + if (isDspPresent(xc)) + { + if (isDspEnabled(xc)) + { + %(op_rd)s; + %(code)s; + } + else + { + fault = new DspStateDisabledFault(); + } + } + else + { + fault = new ReservedInstructionFault(); + } + + if(fault == NoFault) + { + %(op_wb)s; + } + return fault; + } +}}; + +// DspHiLo instruction class execute method template. +def template DspHiLoExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + Fault fault = NoFault; + + %(op_decl)s; + + if (isDspPresent(xc)) + { + if (isDspEnabled(xc)) + { + %(op_rd)s; + %(code)s; + } + else + { + fault = new DspStateDisabledFault(); + } + } + else + { + fault = new ReservedInstructionFault(); + } + + if(fault == NoFault) + { + %(op_wb)s; + //If there are 2 Destination Registers then + //concatenate the values for the traceData + if(traceData && _numDestRegs == 2) { + // FIXME - set the trace value correctly here + //uint64_t hilo_final_val = (uint64_t)HI_RD_SEL << 32 | LO_RD_SEL; + //traceData->setData(hilo_final_val); + } + } + return fault; + } +}}; + +//Outputs to decoder.cc +output decoder {{ +}}; + +output exec {{ + bool isDspEnabled(%(CPU_exec_context)s *xc) + { +#if FULL_SYSTEM + if( bits( xc->readMiscReg(MipsISA::Status), 24, 24 ) == 0 ) + return false; +#else + //printf("Syscall Emulation Mode: isDspEnabled() check defaults to TRUE\n"); +#endif + return true; + } +}}; + +output exec {{ + bool isDspPresent(%(CPU_exec_context)s *xc) + { +#if FULL_SYSTEM + if( bits( xc->readMiscReg(MipsISA::Config3), 10, 10 ) == 0 ) + return false; +#else + //printf("Syscall Emulation Mode: isDspPresent() check defaults to TRUE\n"); +#endif + return true; + } +}}; + +// add code to fetch the DSPControl register +// and write it back after execution, giving +// the instruction the opportunity to modify +// it if necessary +def format DspIntOp(code, *opt_flags) {{ + + decl_code = 'uint32_t dspctl;\n' + decl_code += 'dspctl = DSPControl;\n' + + write_code = 'DSPControl = dspctl;\n' + + code = decl_code + code + write_code + + iop = InstObjParams(name, Name, 'DspIntOp', code, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = DspExecute.subst(iop) +}}; + +// add code to fetch the DSPControl register +// and write it back after execution, giving +// the instruction the opportunity to modify +// it if necessary; also, fetch the appropriate +// HI/LO register pair, based on the AC +// instruction field. + +def format DspHiLoOp(code, *opt_flags) {{ + + decl_code = 'int64_t dspac;\n' + decl_code += 'uint32_t dspctl;\n' + + fetch_code = 'dspctl = DSPControl;\n' + fetch_code += 'dspac = HI_RD_SEL;\n' + fetch_code += 'dspac = dspac << 32 | LO_RD_SEL;\n' + + write_code = 'DSPControl = dspctl;\n' + write_code += 'HI_RD_SEL = dspac<63:32>;\n' + write_code += 'LO_RD_SEL = dspac<31:0>;\n' + + code = decl_code + fetch_code + code + write_code + + iop = InstObjParams(name, Name, 'DspHiLoOp', code, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = DspHiLoExecute.subst(iop) + +}}; + + + diff --git a/src/arch/mips/isa/formats/formats.isa b/src/arch/mips/isa/formats/formats.isa index 4c3eec132..1cff9732f 100644 --- a/src/arch/mips/isa/formats/formats.isa +++ b/src/arch/mips/isa/formats/formats.isa @@ -44,6 +44,9 @@ //Include the integer formats ##include "int.isa" +//Include the DSP integer format +##include "dsp.isa" + //Include the floatOp format ##include "fp.isa" diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa index ac6805cc7..4b340e2e6 100644 --- a/src/arch/mips/isa/formats/fp.isa +++ b/src/arch/mips/isa/formats/fp.isa @@ -87,6 +87,12 @@ output decoder {{ }}; output exec {{ + inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) + { + //@TODO: Implement correct CP0 checks to see if the CP1 + // unit is enable or not + return NoFault; + } //If any operand is Nan return the appropriate QNaN template @@ -145,7 +151,7 @@ output exec {{ uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR); //Write FCSR from FloatRegFile - cpu->tcBase()->setFloatRegBits(FCSR, genInvalidVector(fcsr_bits)); + cpu->tcBase()->setFloatRegOperandBits(FCSR, genInvalidVector(fcsr_bits)); if (traceData) { traceData->setData(mips_nan); } return true; @@ -160,6 +166,7 @@ output exec {{ //Read FCSR from FloatRegFile uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FCSR); + // TODO: Use utility function here fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0); //Write FCSR from FloatRegFile diff --git a/src/arch/mips/isa/formats/int.isa b/src/arch/mips/isa/formats/int.isa index 2f131f6d9..7fa8e4817 100644 --- a/src/arch/mips/isa/formats/int.isa +++ b/src/arch/mips/isa/formats/int.isa @@ -34,6 +34,7 @@ // output header {{ #include + using namespace std; /** * Base class for integer operations. */ @@ -64,12 +65,12 @@ output header {{ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; - class HiLoMiscOp: public HiLoOp + class HiLoRsSelOp: public HiLoOp { protected: /// Constructor - HiLoMiscOp(const char *mnem, MachInst _machInst, OpClass __opClass) : + HiLoRsSelOp(const char *mnem, MachInst _machInst, OpClass __opClass) : HiLoOp(mnem, _machInst, __opClass) { } @@ -77,6 +78,31 @@ output header {{ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; + class HiLoRdSelOp: public HiLoOp + { + protected: + + /// Constructor + HiLoRdSelOp(const char *mnem, MachInst _machInst, OpClass __opClass) : + HiLoOp(mnem, _machInst, __opClass) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; + + class HiLoRdSelValOp: public HiLoOp + { + protected: + + /// Constructor + HiLoRdSelValOp(const char *mnem, MachInst _machInst, OpClass __opClass) : + HiLoOp(mnem, _machInst, __opClass) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; class IntImmOp : public MipsStaticInst { @@ -105,9 +131,7 @@ output header {{ }}; -// HiLo instruction class execute method template. -// Mainly to get instruction trace data to print out -// correctly +// HiLo instruction class execute method template. def template HiLoExecute {{ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { @@ -121,12 +145,58 @@ def template HiLoExecute {{ if(fault == NoFault) { %(op_wb)s; - //If there are 2 Destination Registers then - //concatenate the values for the traceData - if(traceData && _numDestRegs == 2) { - uint64_t hilo_final_val = (uint64_t)HI << 32 | LO; - traceData->setData(hilo_final_val); - } + } + return fault; + } +}}; + +// HiLoRsSel instruction class execute method template. +def template HiLoRsSelExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + Fault fault = NoFault; + + %(op_decl)s; + + if( ACSRC > 0 && !isDspEnabled(xc) ) + { + fault = new DspStateDisabledFault(); + } + else + { + %(op_rd)s; + %(code)s; + } + + if(fault == NoFault) + { + %(op_wb)s; + } + return fault; + } +}}; + +// HiLoRdSel instruction class execute method template. +def template HiLoRdSelExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + Fault fault = NoFault; + + %(op_decl)s; + + if( ACDST > 0 && !isDspEnabled(xc) ) + { + fault = new DspStateDisabledFault(); + } + else + { + %(op_rd)s; + %(code)s; + } + + if(fault == NoFault) + { + %(op_wb)s; } return fault; } @@ -181,7 +251,37 @@ output decoder {{ return ss.str(); } - std::string HiLoMiscOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const + std::string HiLoRsSelOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + std::stringstream ss; + + ccprintf(ss, "%-10s ", mnemonic); + + if (_numDestRegs > 0 && _destRegIdx[0] < 32) { + printReg(ss, _destRegIdx[0]); + } else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) { + printReg(ss, _srcRegIdx[0]); + } + + return ss.str(); + } + + std::string HiLoRdSelOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + std::stringstream ss; + + ccprintf(ss, "%-10s ", mnemonic); + + if (_numDestRegs > 0 && _destRegIdx[0] < 32) { + printReg(ss, _destRegIdx[0]); + } else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) { + printReg(ss, _srcRegIdx[0]); + } + + return ss.str(); + } + + std::string HiLoRdSelValOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; @@ -239,26 +339,43 @@ def format IntImmOp(code, *opt_flags) {{ exec_output = BasicExecute.subst(iop) }}; -def format HiLoOp(code, *opt_flags) {{ - code += 'HI = val<63:32>;\n' - code += 'LO = val<31:0>;\n' - - iop = InstObjParams(name, Name, 'HiLoOp', code, opt_flags) +def format HiLoRsSelOp(code, *opt_flags) {{ + iop = InstObjParams(name, Name, 'HiLoRsSelOp', code, opt_flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) decode_block = BasicDecode.subst(iop) - exec_output = HiLoExecute.subst(iop) + exec_output = HiLoRsSelExecute.subst(iop) }}; -def format HiLoMiscOp(code, *opt_flags) {{ - iop = InstObjParams(name, Name, 'HiLoMiscOp', code, opt_flags) +def format HiLoRdSelOp(code, *opt_flags) {{ + iop = InstObjParams(name, Name, 'HiLoRdSelOp', code, opt_flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) decode_block = BasicDecode.subst(iop) - exec_output = BasicExecute.subst(iop) + exec_output = HiLoRdSelExecute.subst(iop) }}; +def format HiLoRdSelValOp(code, *opt_flags) {{ + if '.sd' in code: + code = 'int64_t ' + code + elif '.ud' in code: + code = 'uint64_t ' + code + code += 'HI_RD_SEL = val<63:32>;\n' + code += 'LO_RD_SEL = val<31:0>;\n' + iop = InstObjParams(name, Name, 'HiLoRdSelOp', code, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = HiLoRdSelExecute.subst(iop) +}}; +def format HiLoOp(code, *opt_flags) {{ + iop = InstObjParams(name, Name, 'HiLoOp', code, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = HiLoExecute.subst(iop) +}}; diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa index df80e7a1f..c8e85a754 100644 --- a/src/arch/mips/isa/formats/mem.isa +++ b/src/arch/mips/isa/formats/mem.isa @@ -69,6 +69,8 @@ output header {{ const StaticInstPtr &eaCompInst() const { return eaCompPtr; } const StaticInstPtr &memAccInst() const { return memAccPtr; } + + unsigned memAccFlags() { return memAccessFlags; } }; /** @@ -108,6 +110,37 @@ output decoder {{ flags[IsFloating] ? FD : RD, RS, RT); } + +}}; + +output exec {{ + /** return data in cases where there the size of data is only + known in the packet + */ + uint64_t getStoreData(Packet *packet) { + switch (packet->getSize()) + { + case 8: + return packet->get(); + + case 16: + return packet->get(); + + case 32: + return packet->get(); + + case 864: + return packet->get(); + + default: + std::cerr << "bad store data size = " << packet->getSize() << std::endl; + + assert(0); + return 0; + } + } + + }}; def template LoadStoreDeclare {{ @@ -125,7 +158,7 @@ def template LoadStoreDeclare {{ { public: /// Constructor - EAComp(MachInst machInst); + EAComp(ExtMachInst machInst); %(BasicExecDeclare)s }; @@ -137,7 +170,7 @@ def template LoadStoreDeclare {{ { public: /// Constructor - MemAcc(MachInst machInst); + MemAcc(ExtMachInst machInst); %(BasicExecDeclare)s }; @@ -145,13 +178,15 @@ def template LoadStoreDeclare {{ public: /// Constructor. - %(class_name)s(MachInst machInst); + %(class_name)s(ExtMachInst machInst); %(BasicExecDeclare)s %(InitiateAccDeclare)s %(CompleteAccDeclare)s + + %(MemAccSizeDeclare)s }; }}; @@ -162,15 +197,18 @@ def template InitiateAccDeclare {{ def template CompleteAccDeclare {{ - Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; + Fault completeAcc(Packet *, %(CPU_exec_context)s *, Trace::InstRecord *) const; }}; +def template MemAccSizeDeclare {{ + int memAccSize(%(CPU_exec_context)s *xc); +}}; def template EACompConstructor {{ /** TODO: change op_class to AddrGenOp or something (requires * creating new member of OpClass enum in op_class.hh, updating * config files, etc.). */ - inline %(class_name)s::EAComp::EAComp(MachInst machInst) + inline %(class_name)s::EAComp::EAComp(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp) { %(constructor)s; @@ -179,7 +217,7 @@ def template EACompConstructor {{ def template MemAccConstructor {{ - inline %(class_name)s::MemAcc::MemAcc(MachInst machInst) + inline %(class_name)s::MemAcc::MemAcc(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s) { %(constructor)s; @@ -188,7 +226,7 @@ def template MemAccConstructor {{ def template LoadStoreConstructor {{ - inline %(class_name)s::%(class_name)s(MachInst machInst) + inline %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, new EAComp(machInst), new MemAcc(machInst)) { @@ -210,8 +248,8 @@ def template EACompExecute {{ %(op_rd)s; %(ea_code)s; + // NOTE: Trace Data is written using execute or completeAcc templates if (fault == NoFault) { - %(op_wb)s; xc->setEA(EA); } @@ -227,19 +265,16 @@ def template LoadMemAccExecute {{ Addr EA; Fault fault = NoFault; - %(fp_enable_check)s; %(op_decl)s; %(op_rd)s; + EA = xc->getEA(); - if (fault == NoFault) { - fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); - %(memacc_code)s; - } + fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); - if (fault == NoFault) { - %(op_wb)s; - } + %(memacc_code)s; + + // NOTE: Write back data using execute or completeAcc templates return fault; } @@ -292,9 +327,8 @@ def template LoadInitiateAcc {{ } }}; - def template LoadCompleteAcc {{ - Fault %(class_name)s::completeAcc(PacketPtr pkt, + Fault %(class_name)s::completeAcc(Packet *pkt, %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { @@ -302,6 +336,7 @@ def template LoadCompleteAcc {{ %(fp_enable_check)s; %(op_decl)s; + %(op_rd)s; Mem = pkt->get(); @@ -318,6 +353,15 @@ def template LoadCompleteAcc {{ }}; + +def template LoadStoreMemAccSize {{ + int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc) + { + // Return the memory access size in bytes + return (%(mem_acc_size)d / 8); + } +}}; + def template StoreMemAccExecute {{ Fault %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, @@ -325,10 +369,12 @@ def template StoreMemAccExecute {{ { Addr EA; Fault fault = NoFault; + uint64_t write_result = 0; %(fp_enable_check)s; %(op_decl)s; %(op_rd)s; + EA = xc->getEA(); if (fault == NoFault) { @@ -337,16 +383,9 @@ def template StoreMemAccExecute {{ if (fault == NoFault) { fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, - memAccessFlags, NULL); - if (traceData) { traceData->setData(Mem); } - } - - if (fault == NoFault) { - %(postacc_code)s; - } - - if (fault == NoFault) { - %(op_wb)s; + memAccessFlags, &write_result); + // @NOTE: Need to Call Complete Access to Set Trace Data + //if (traceData) { traceData->setData(Mem); } } return fault; @@ -389,13 +428,13 @@ def template StoreCondMemAccExecute {{ } }}; - def template StoreExecute {{ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { Addr EA; Fault fault = NoFault; + uint64_t write_result = 0; %(fp_enable_check)s; %(op_decl)s; @@ -408,7 +447,7 @@ def template StoreExecute {{ if (fault == NoFault) { fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, - memAccessFlags, NULL); + memAccessFlags, &write_result); if (traceData) { traceData->setData(Mem); } } @@ -487,7 +526,7 @@ def template StoreInitiateAcc {{ def template StoreCompleteAcc {{ - Fault %(class_name)s::completeAcc(PacketPtr pkt, + Fault %(class_name)s::completeAcc(Packet *pkt, %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { @@ -502,6 +541,8 @@ def template StoreCompleteAcc {{ if (fault == NoFault) { %(op_wb)s; + + if (traceData) { traceData->setData(getStoreData(pkt)); } } return fault; @@ -509,7 +550,7 @@ def template StoreCompleteAcc {{ }}; def template StoreCondCompleteAcc {{ - Fault %(class_name)s::completeAcc(PacketPtr pkt, + Fault %(class_name)s::completeAcc(Packet *pkt, %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { @@ -584,7 +625,7 @@ def template MiscInitiateAcc {{ def template MiscCompleteAcc {{ - Fault %(class_name)s::completeAcc(PacketPtr pkt, + Fault %(class_name)s::completeAcc(Packet *pkt, %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { @@ -594,6 +635,15 @@ def template MiscCompleteAcc {{ } }}; + +def template MiscMemAccSize {{ + int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc) + { + panic("Misc instruction does not support split access method!"); + return 0; + } +}}; + def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, mem_flags = [], inst_flags = []) {{ (header_output, decoder_output, decode_block, exec_output) = \ @@ -650,6 +700,7 @@ def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; decl_code += '\tbyte_offset ^= 3;\n' decl_code += '#endif\n' decl_code += 'fault = xc->read(EA, (uint32_t&)mem_word, memAccessFlags);\n' + #decl_code += 'xc->readFunctional(EA,(uint32_t&)mem_word);' memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n' (header_output, decoder_output, decode_block, exec_output) = \ diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa index d7240335e..b3520050a 100644 --- a/src/arch/mips/isa/formats/mt.isa +++ b/src/arch/mips/isa/formats/mt.isa @@ -37,46 +37,185 @@ output header {{ /** * Base class for MIPS MT ASE operations. */ - class MT : public MipsStaticInst + class MTOp : public MipsStaticInst { protected: /// Constructor - MT(const char *mnem, MachInst _machInst, OpClass __opClass) : - MipsStaticInst(mnem, _machInst, __opClass) + MTOp(const char *mnem, MachInst _machInst, OpClass __opClass) : + MipsStaticInst(mnem, _machInst, __opClass), user_mode(false) { } - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + + bool user_mode; + }; + + class MTUserModeOp : public MTOp + { + protected: + + /// Constructor + MTUserModeOp(const char *mnem, MachInst _machInst, OpClass __opClass) : + MTOp(mnem, _machInst, __opClass) + { + user_mode = true; + } + + //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; }}; output decoder {{ - //Edit This Template When MT is Implemented - std::string MT::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - return "Disassembly of MT instruction\n"; + std::string MTOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + std::stringstream ss; + + if (mnemonic == "mttc0" || mnemonic == "mftc0") { + ccprintf(ss, "%-10s r%d, r%d, %d", mnemonic, RT, RD, SEL); + } else if (mnemonic == "mftgpr") { + ccprintf(ss, "%-10s r%d, r%d", mnemonic, RD, RT); + } else { + ccprintf(ss, "%-10s r%d, r%d", mnemonic, RT, RD); } + + return ss.str(); + } }}; -def template MTExecute {{ - //Edit This Template When MT is Implemented +output exec {{ + void getThrRegExValues(%(CPU_exec_context)s *xc, unsigned &vpe_conf0, unsigned &tc_bind_mt, unsigned &tc_bind, unsigned &vpe_control, unsigned &mvp_conf0) + { + vpe_conf0 = xc->readMiscReg(VPEConf0); + tc_bind_mt = xc->readRegOtherThread(TCBind + Ctrl_Base_DepTag); + tc_bind = xc->readMiscReg(TCBind); + vpe_control = xc->readMiscReg(VPEControl); + mvp_conf0 = xc->readMiscReg(MVPConf0); + } + + void getMTExValues(%(CPU_exec_context)s *xc, unsigned &config3) + { + config3 = xc->readMiscReg(Config3_MT); + } +}}; + +def template ThreadRegisterExecute {{ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { - //Write the resulting state to the execution context + Fault fault = NoFault; + int64_t data; + %(op_decl)s; + %(op_rd)s; + + unsigned vpe_conf0, tc_bind_mt, tc_bind, vpe_control, mvp_conf0; + + getThrRegExValues(xc, vpe_conf0, tc_bind_mt, tc_bind, vpe_control, mvp_conf0); + + if (isCoprocessorEnabled(xc, 0)) { + if (bits(vpe_conf0, VPEC0_MVP) == 0 && + bits(tc_bind_mt, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO) != + bits(tc_bind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO)) { + data = -1; + } else if (bits(vpe_control, VPEC_TARG_TC_HI, VPEC_TARG_TC_LO) > + bits(mvp_conf0, MVPC0_PTC_HI, MVPC0_PTC_LO)) { + data = -1; + } else { + int top_bit = 0; + int bottom_bit = 0; + + if (MT_H == 1) { + top_bit = 63; + bottom_bit = 32; + } else { + top_bit = 31; + bottom_bit = 0; + } + + %(code)s; + } + } else { + fault = new CoprocessorUnusableFault(); + } + + if(fault == NoFault) + { %(op_wb)s; + } - //Call into the trap handler with the appropriate fault - return No_Fault; + return fault; + } +}}; + +def template MTExecute{{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + Fault fault = NoFault; + %(op_decl)s; + %(op_rd)s; + + unsigned config3; + + getMTExValues(xc, config3); + + if (isCoprocessorEnabled(xc, 0)) { + if (bits(config3, CFG3_MT) == 1) { + %(code)s; + } else { + fault = new ReservedInstructionFault(); + } + } else { + fault = new CoprocessorUnusableFault(); + } + + if(fault == NoFault) + { + %(op_wb)s; + } + return fault; } }}; // Primary format for integer operate instructions: -def format MipsMT() {{ - code = 'panic(\"Mips MT Is Currently Unimplemented.\");\n' - iop = InstObjParams(name, Name, 'MT', code) +def format MT_Control(code, *opt_flags) {{ + inst_flags = ('IsNonSpeculative', ) + op_type = 'MTOp' + + for x in opt_flags: + if x == 'UserMode': + op_type = 'MTUserModeOp' + else: + inst_flags += (x, ) + + iop = InstObjParams(name, Name, op_type, code, inst_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = MTExecute.subst(iop) +}}; + +def format MT_MFTR(code, *flags) {{ + flags += ('IsNonSpeculative', ) +# code = 'std::cerr << curTick << \": T\" << xc->tcBase()->getThreadNum() << \": Executing MT INST: ' + name + '\" << endl;\n' + code + + code += 'if (MT_H == 1) {\n' + code += 'data = bits(data, top_bit, bottom_bit);\n' + code += '}\n' + code += 'Rd = data;\n' + + iop = InstObjParams(name, Name, 'MTOp', code, flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = ThreadRegisterExecute.subst(iop) +}}; + +def format MT_MTTR(code, *flags) {{ + flags += ('IsNonSpeculative', ) +# code = 'std::cerr << curTick << \": T\" << xc->tcBase()->getThreadNum() << \": Executing MT INST: ' + name + '\" << endl;\n' + code + iop = InstObjParams(name, Name, 'MTOp', code, flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) decode_block = BasicDecode.subst(iop) - exec_output = BasicExecute.subst(iop) + exec_output = ThreadRegisterExecute.subst(iop) }}; diff --git a/src/arch/mips/isa/formats/tlbop.isa b/src/arch/mips/isa/formats/tlbop.isa index dbfbb8ce1..b6db7864f 100644 --- a/src/arch/mips/isa/formats/tlbop.isa +++ b/src/arch/mips/isa/formats/tlbop.isa @@ -70,7 +70,9 @@ def template TlbOpExecute {{ // Primary format for integer operate instructions: def format TlbOp(code, *opt_flags) {{ - iop = InstObjParams(name, Name, 'MipsStaticInst', code, opt_flags) + orig_code = code + cblk = code + iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) decode_block = BasicDecodeWithMnemonic.subst(iop) diff --git a/src/arch/mips/isa/formats/util.isa b/src/arch/mips/isa/formats/util.isa index 884e6f727..eea616568 100644 --- a/src/arch/mips/isa/formats/util.isa +++ b/src/arch/mips/isa/formats/util.isa @@ -88,7 +88,6 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, + completeAccTemplate.subst(iop)) }}; - output header {{ std::string inst2string(MachInst machInst); }}; @@ -97,7 +96,7 @@ output decoder {{ std::string inst2string(MachInst machInst) { - std::string str = ""; + string str = ""; uint32_t mask = 0x80000000; for(int i=0; i < 32; i++) { @@ -114,40 +113,3 @@ std::string inst2string(MachInst machInst) } }}; -output exec {{ - - using namespace MipsISA; - - /// CLEAR ALL CPU INST/EXE HAZARDS - inline void - clear_exe_inst_hazards() - { - //CODE HERE - } - - - /// Check "FP enabled" machine status bit. Called when executing any FP - /// instruction in full-system mode. - /// @retval Full-system mode: NoFault if FP is enabled, FenFault - /// if not. Non-full-system mode: always returns NoFault. -#if FULL_SYSTEM - inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) - { - Fault fault = NoFault; // dummy... this ipr access should not fault - if (!Mips34k::ICSR_FPE(xc->readIpr(MipsISA::IPR_ICSR, fault))) { - fault = FloatEnableFault; - } - return fault; - } -#else - inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) - { - return NoFault; - } -#endif - - - -}}; - - diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa index 274fdcaa1..0e0cf44eb 100644 --- a/src/arch/mips/isa/includes.isa +++ b/src/arch/mips/isa/includes.isa @@ -44,19 +44,23 @@ output header {{ }}; output decoder {{ -#include -#if defined(linux) -#include -#endif - -#include "arch/mips/faults.hh" #include "arch/mips/isa_traits.hh" -#include "arch/mips/isa_traits.hh" -#include "arch/mips/isa_traits.hh" -#include "arch/mips/utility.hh" #include "base/cprintf.hh" #include "base/loader/symtab.hh" #include "cpu/thread_context.hh" +#include "arch/mips/faults.hh" +#include "arch/mips/isa_traits.hh" +#include "arch/mips/pra_constants.hh" +#include "arch/mips/dt_constants.hh" +#include "arch/mips/mt_constants.hh" +#include "arch/mips/utility.hh" +#include "arch/mips/dsp.hh" +#include "mem/packet.hh" + +#include +#if defined(linux) +#include +#endif using namespace MipsISA; }}; @@ -65,20 +69,25 @@ output exec {{ #include "arch/mips/faults.hh" #include "arch/mips/isa_traits.hh" #include "arch/mips/utility.hh" +#include "arch/mips/dsp.hh" +#include "arch/mips/pra_constants.hh" +#include "arch/mips/dt_constants.hh" +#include "arch/mips/mt_constants.hh" #include #if defined(linux) #include #endif -#ifdef FULL_SYSTEM -//#include "arch/alpha/pseudo_inst.hh" -#endif #include "cpu/base.hh" #include "cpu/exetrace.hh" + #include "mem/packet.hh" #include "mem/packet_access.hh" + #include "sim/sim_exit.hh" +#include "sim/eventq.hh" +#include "sim/sim_events.hh" using namespace MipsISA; }}; diff --git a/src/arch/mips/isa/operands.isa b/src/arch/mips/isa/operands.isa index 3843dc053..b89eb5249 100644 --- a/src/arch/mips/isa/operands.isa +++ b/src/arch/mips/isa/operands.isa @@ -48,16 +48,37 @@ def operands {{ 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2), 'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3), + #Immediate Value operand + 'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3), + #Operands used for Link or Syscall Insts 'R31': ('IntReg', 'uw','31','IsInteger', 4), 'R2': ('IntReg', 'uw','2', 'IsInteger', 5), #Special Integer Reg operands - 'HI': ('IntReg', 'uw','MipsISA::HI', 'IsInteger', 6), - 'LO': ('IntReg', 'uw','MipsISA::LO', 'IsInteger', 7), + 'LO0': ('IntReg', 'uw','MipsISA::LO', 'IsInteger', 6), + 'HI0': ('IntReg', 'uw','MipsISA::HI', 'IsInteger', 7), - #Immediate Value operand - 'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3), + #Bitfield-dependent HI/LO Register Access + 'LO_RD_SEL': ('IntReg','uw','MipsISA::DSPLo0 + ACDST*3', None, 6), + 'HI_RD_SEL': ('IntReg','uw','MipsISA::DSPHi0 + ACDST*3', None, 7), + 'LO_RS_SEL': ('IntReg','uw','MipsISA::DSPLo0 + ACSRC*3', None, 6), + 'HI_RS_SEL': ('IntReg','uw','MipsISA::DSPHi0 + ACSRC*3', None, 7), + + #DSP Special Purpose Integer Operands + 'DSPControl': ('IntReg', 'uw', 'MipsISA::DSPControl', None, 8), + 'DSPLo0': ('IntReg', 'uw', 'MipsISA::LO', None, 1), + 'DSPHi0': ('IntReg', 'uw', 'MipsISA::HI', None, 1), + 'DSPACX0': ('IntReg', 'uw', 'MipsISA::DSPACX0', None, 1), + 'DSPLo1': ('IntReg', 'uw', 'MipsISA::DSPLo1', None, 1), + 'DSPHi1': ('IntReg', 'uw', 'MipsISA::DSPHi1', None, 1), + 'DSPACX1': ('IntReg', 'uw', 'MipsISA::DSPACX1', None, 1), + 'DSPLo2': ('IntReg', 'uw', 'MipsISA::DSPLo2', None, 1), + 'DSPHi2': ('IntReg', 'uw', 'MipsISA::DSPHi2', None, 1), + 'DSPACX2': ('IntReg', 'uw', 'MipsISA::DSPACX2', None, 1), + 'DSPLo3': ('IntReg', 'uw', 'MipsISA::DSPLo3', None, 1), + 'DSPHi3': ('IntReg', 'uw', 'MipsISA::DSPHi3', None, 1), + 'DSPACX3': ('IntReg', 'uw', 'MipsISA::DSPACX3', None, 1), #Floating Point Reg Operands 'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1), @@ -65,14 +86,14 @@ def operands {{ 'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3), 'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3), - #Special Floating Point Control Reg Operands + #Special Purpose Floating Point Control Reg Operands 'FIR': ('FloatReg', 'uw', 'MipsISA::FIR', 'IsFloating', 1), 'FCCR': ('FloatReg', 'uw', 'MipsISA::FCCR', 'IsFloating', 2), 'FEXR': ('FloatReg', 'uw', 'MipsISA::FEXR', 'IsFloating', 3), 'FENR': ('FloatReg', 'uw', 'MipsISA::FENR', 'IsFloating', 3), 'FCSR': ('FloatReg', 'uw', 'MipsISA::FCSR', 'IsFloating', 3), - #Operands For Paired Singles FP Operations + #Operands For Paired Singles FP Operations 'Fd1': ('FloatReg', 'sf', 'FD', 'IsFloating', 4), 'Fd2': ('FloatReg', 'sf', 'FD+1', 'IsFloating', 4), 'Fs1': ('FloatReg', 'sf', 'FS', 'IsFloating', 5), @@ -82,10 +103,44 @@ def operands {{ 'Fr1': ('FloatReg', 'sf', 'FR', 'IsFloating', 7), 'Fr2': ('FloatReg', 'sf', 'FR+1', 'IsFloating', 7), + #Status Control Reg + 'Status': ('ControlReg', 'uw', 'MipsISA::Status', None, 1), + + #Special cases for when a Control Register Access is dependent on + #a combination of bitfield indices (handles MTCO & MFCO) + 'CP0_RD_SEL': ('ControlReg', 'uw', 'RD << 3 | SEL', None, 1), + + #MT Control Regs + 'MVPConf0': ('ControlReg', 'uw', 'MipsISA::MVPConf0', None, 1), + 'MVPControl': ('ControlReg', 'uw', 'MipsISA::MVPControl', None, 1), + 'TCBind': ('ControlReg', 'uw', 'MipsISA::TCBind', None, 1), + 'TCStatus': ('ControlReg', 'uw', 'MipsISA::TCStatus', None, 1), + 'TCRestart': ('ControlReg', 'uw', 'MipsISA::TCRestart', None, 1), + 'VPEConf0': ('ControlReg', 'uw', 'MipsISA::VPEConf0', None, 1), + 'VPEControl': ('ControlReg', 'uw', 'MipsISA::VPEControl', None, 1), + 'YQMask': ('ControlReg', 'uw', 'MipsISA::YQMask', None, 1), + + # named bitfields of Control Regs + 'Status_IE': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), + 'Status_ERL': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), + 'Status_EXL': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), + 'Status_CU3': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), + 'Status_CU2': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), + 'Status_CU1': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), + 'Status_CU0': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), + 'SRSCtl_HSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4), + 'SRSCtl_PSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4), + 'SRSCtl_CSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4), + 'Config_AR': ('ControlBitfield', 'uw', 'MipsISA::Config', None, 3), + + # named bitfields of Debug Regs + 'Debug_DM': ('ControlBitfield', 'uw', 'MipsISA::Debug', None, 1), + 'Debug_IEXI': ('ControlBitfield', 'uw', 'MipsISA::Debug', None, 1), + #Memory Operand 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), #Program Counter Operands - 'NPC': ('NPC', 'uw', None, ( None, None, 'IsControl' ), 4), - 'NNPC':('NNPC', 'uw', None, ( None, None, 'IsControl' ), 4) + 'NPC': ('NPC', 'uw', None, 'IsControl', 4), + 'NNPC':('NNPC', 'uw', None, 'IsControl', 4) }}; -- cgit v1.2.3