From 68e470f78aac9fc5ea15f0840deda0972bef7666 Mon Sep 17 00:00:00 2001
From: Korey Sewell <ksewell@umich.edu>
Date: Fri, 9 Jun 2006 03:57:25 -0400
Subject: Merging in a month of changes

src/arch/isa_parser.py:
    Sign extend bit if you read int reg that is greater than default size
src/arch/mips/SConscript:
src/arch/mips/faults.cc:
src/arch/mips/faults.hh:
src/arch/mips/isa/base.isa:
src/arch/mips/isa/bitfields.isa:
src/arch/mips/isa/decoder.isa:
src/arch/mips/isa/formats/basic.isa:
src/arch/mips/isa/formats/branch.isa:
src/arch/mips/isa/formats/formats.isa:
src/arch/mips/isa/formats/fp.isa:
src/arch/mips/isa/formats/int.isa:
src/arch/mips/isa/formats/mem.isa:
src/arch/mips/isa/formats/noop.isa:
src/arch/mips/isa/formats/tlbop.isa:
src/arch/mips/isa/formats/trap.isa:
src/arch/mips/isa/formats/unimp.isa:
src/arch/mips/isa/formats/unknown.isa:
src/arch/mips/isa/formats/util.isa:
src/arch/mips/isa/includes.isa:
src/arch/mips/isa/main.isa:
src/arch/mips/isa/operands.isa:
src/arch/mips/isa_traits.cc:
src/arch/mips/linux/process.cc:
src/arch/mips/linux/process.hh:
src/arch/mips/process.cc:
src/arch/mips/process.hh:
src/arch/mips/regfile/float_regfile.hh:
src/arch/mips/utility.hh:
    1 month of changes!
src/arch/mips/isa/formats/control.isa:
    control formats
src/arch/mips/isa/formats/mt.isa:
    mips mt format
src/arch/mips/utility.cc:
    utility functions

--HG--
extra : convert_revision : c1332cb5ce08b464b99fbf04f4a5cac312898784
---
 src/arch/mips/isa_traits.cc | 73 ++-------------------------------------------
 1 file changed, 2 insertions(+), 71 deletions(-)

(limited to 'src/arch/mips/isa_traits.cc')

diff --git a/src/arch/mips/isa_traits.cc b/src/arch/mips/isa_traits.cc
index 056c8baff..9f3817a60 100644
--- a/src/arch/mips/isa_traits.cc
+++ b/src/arch/mips/isa_traits.cc
@@ -42,6 +42,7 @@ using namespace std;
 void
 MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest)
 {
+    panic("Copy Regs Not Implemented Yet\n");
     /*fpcr = xc->readMiscReg(MipsISA::Fpcr_DepTag);
     uniq = xc->readMiscReg(MipsISA::Uniq_DepTag);
     lock_flag = xc->readMiscReg(MipsISA::Lock_Flag_DepTag);
@@ -55,6 +56,7 @@ MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest)
 void
 MipsISA::MiscRegFile::copyMiscRegs(ThreadContext *tc)
 {
+    panic("Copy Misc. Regs Not Implemented Yet\n");
     /*fpcr = xc->readMiscReg(MipsISA::Fpcr_DepTag);
     uniq = xc->readMiscReg(MipsISA::Uniq_DepTag);
     lock_flag = xc->readMiscReg(MipsISA::Lock_Flag_DepTag);
@@ -63,77 +65,6 @@ MipsISA::MiscRegFile::copyMiscRegs(ThreadContext *tc)
     #endif*/
 }
 
-uint64_t
-MipsISA::fpConvert(double fp_val, ConvertType cvt_type)
-{
-
-    switch (cvt_type)
-    {
-      case SINGLE_TO_DOUBLE:
-        double sdouble_val = fp_val;
-        void  *sdouble_ptr = &sdouble_val;
-        uint64_t sdp_bits  = *(uint64_t *) sdouble_ptr;
-        return sdp_bits;
-
-      case SINGLE_TO_WORD:
-        int32_t sword_val  = (int32_t) fp_val;
-        void  *sword_ptr   = &sword_val;
-        uint64_t sword_bits= *(uint32_t *) sword_ptr;
-        return sword_bits;
-
-      case WORD_TO_SINGLE:
-        float wfloat_val   = fp_val;
-        void  *wfloat_ptr  = &wfloat_val;
-        uint64_t wfloat_bits = *(uint32_t *) wfloat_ptr;
-        return wfloat_bits;
-
-      case WORD_TO_DOUBLE:
-        double wdouble_val = fp_val;
-        void  *wdouble_ptr = &wdouble_val;
-        uint64_t wdp_bits  = *(uint64_t *) wdouble_ptr;
-        return wdp_bits;
-
-      default:
-        panic("Invalid Floating Point Conversion Type (%d). See \"types.hh\" for List of Conversions\n",cvt_type);
-        return 0;
-    }
-}
-
-double
-MipsISA::roundFP(double val, int digits)
-{
-    double digit_offset = pow(10.0,digits);
-    val = val * digit_offset;
-    val = val + 0.5;
-    val = floor(val);
-    val = val / digit_offset;
-    return val;
-}
-
-double
-MipsISA::truncFP(double val)
-{
-    int trunc_val = (int) val;
-    return (double) trunc_val;
-}
-
-bool
-MipsISA::getFPConditionCode(uint32_t fcsr_reg, int cc)
-{
-    //uint32_t cc_bits = xc->readFloatReg(35);
-    return false;//regFile.floatRegfile.getConditionCode(cc);
-}
-
-uint32_t
-MipsISA::makeCCVector(uint32_t fcsr, int num, bool val)
-{
-    int shift = (num == 0) ? 22 : num + 23;
-
-    fcsr = fcsr | (val << shift);
-
-    return fcsr;
-}
-
 #if FULL_SYSTEM
 
 static inline Addr
-- 
cgit v1.2.3