From 269259004943b80916ec9b6354f2fc00c811c88b Mon Sep 17 00:00:00 2001
From: Korey Sewell <ksewell@umich.edu>
Date: Tue, 13 Nov 2007 16:58:16 -0500
Subject: Add in files from merge-bare-iron, get them compiling in FS and SE
 mode

--HG--
extra : convert_revision : d4e19afda897bc3797868b40469ce2ec7ec7d251
---
 src/arch/mips/mips_core_specific.hh | 62 +++++++++++++++++++++++++++++++++++++
 1 file changed, 62 insertions(+)
 create mode 100644 src/arch/mips/mips_core_specific.hh

(limited to 'src/arch/mips/mips_core_specific.hh')

diff --git a/src/arch/mips/mips_core_specific.hh b/src/arch/mips/mips_core_specific.hh
new file mode 100644
index 000000000..ff517316e
--- /dev/null
+++ b/src/arch/mips/mips_core_specific.hh
@@ -0,0 +1,62 @@
+/*
+ * Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
+ *
+ * This software is part of the M5 simulator.
+ *
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+ * TO THESE TERMS AND CONDITIONS.
+ *
+ * Permission is granted to use, copy, create derivative works and
+ * distribute this software and such derivative works for any purpose,
+ * so long as (1) the copyright notice above, this grant of permission,
+ * and the disclaimer below appear in all copies and derivative works
+ * made, (2) the copyright notice above is augmented as appropriate to
+ * reflect the addition of any new copyrightable work in a derivative
+ * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ * Authors: Jaidev Patwardhan
+ *
+ */
+
+
+#ifndef __ARCH_MIPS_CORE_SPECIFIC_HH__
+#define __ARCH_MIPS_CORE_SPECIFIC_HH__
+
+#include "arch/mips/isa_traits.hh"
+
+namespace MipsCore {
+
+//It seems like a safe assumption MipsCore only applies to mips
+using namespace MipsISA;
+
+const unsigned VABits = 32;
+const unsigned PABits = 32; // Is this correct?
+const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
+const Addr VAddrUnImplMask = ~VAddrImplMask;
+inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
+inline Addr VAddrVPN(Addr a) { return a >> MipsISA::PageShift; }
+inline Addr VAddrOffset(Addr a) { return a & MipsISA::PageOffset; }
+
+const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
+
+
+/* namespace MipsCore */ }
+
+#endif // __ARCH_MIPS_CORE_SPECIFIC_HH__
-- 
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