From 1c8dfd92543aba5f49e464b17e7e8143fc01a58c Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Tue, 12 May 2009 15:01:13 -0400 Subject: inorder-alpha-port: initial inorder support of ALPHA Edit AlphaISA to support the inorder model. Mostly alternate constructor functions and also a few skeleton multithreaded support functions * * * Remove namespace from header file. Causes compiler issues that are hard to find * * * Separate the TLB from the CPU and allow it to live in the TLBUnit resource. Give CPU accessor functions for access and also bind at construction time * * * Expose memory access size and flags through instruction object (temporarily memAccSize and memFlags to get TLB stuff working.) --- src/arch/mips/regfile/misc_regfile.hh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/arch/mips/regfile') diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh index c611d94cc..0daf8f718 100644 --- a/src/arch/mips/regfile/misc_regfile.hh +++ b/src/arch/mips/regfile/misc_regfile.hh @@ -69,7 +69,7 @@ namespace MipsISA public: MiscRegFile(); - MiscRegFile(BaseCPU *cpu); + MiscRegFile(BaseCPU *_cpu); void init(); -- cgit v1.2.3