From 68e470f78aac9fc5ea15f0840deda0972bef7666 Mon Sep 17 00:00:00 2001
From: Korey Sewell <ksewell@umich.edu>
Date: Fri, 9 Jun 2006 03:57:25 -0400
Subject: Merging in a month of changes

src/arch/isa_parser.py:
    Sign extend bit if you read int reg that is greater than default size
src/arch/mips/SConscript:
src/arch/mips/faults.cc:
src/arch/mips/faults.hh:
src/arch/mips/isa/base.isa:
src/arch/mips/isa/bitfields.isa:
src/arch/mips/isa/decoder.isa:
src/arch/mips/isa/formats/basic.isa:
src/arch/mips/isa/formats/branch.isa:
src/arch/mips/isa/formats/formats.isa:
src/arch/mips/isa/formats/fp.isa:
src/arch/mips/isa/formats/int.isa:
src/arch/mips/isa/formats/mem.isa:
src/arch/mips/isa/formats/noop.isa:
src/arch/mips/isa/formats/tlbop.isa:
src/arch/mips/isa/formats/trap.isa:
src/arch/mips/isa/formats/unimp.isa:
src/arch/mips/isa/formats/unknown.isa:
src/arch/mips/isa/formats/util.isa:
src/arch/mips/isa/includes.isa:
src/arch/mips/isa/main.isa:
src/arch/mips/isa/operands.isa:
src/arch/mips/isa_traits.cc:
src/arch/mips/linux/process.cc:
src/arch/mips/linux/process.hh:
src/arch/mips/process.cc:
src/arch/mips/process.hh:
src/arch/mips/regfile/float_regfile.hh:
src/arch/mips/utility.hh:
    1 month of changes!
src/arch/mips/isa/formats/control.isa:
    control formats
src/arch/mips/isa/formats/mt.isa:
    mips mt format
src/arch/mips/utility.cc:
    utility functions

--HG--
extra : convert_revision : c1332cb5ce08b464b99fbf04f4a5cac312898784
---
 src/arch/mips/regfile/float_regfile.hh | 45 +++++++++++++++++-----------------
 1 file changed, 22 insertions(+), 23 deletions(-)

(limited to 'src/arch/mips/regfile')

diff --git a/src/arch/mips/regfile/float_regfile.hh b/src/arch/mips/regfile/float_regfile.hh
index 013aa01c7..d1a60298a 100644
--- a/src/arch/mips/regfile/float_regfile.hh
+++ b/src/arch/mips/regfile/float_regfile.hh
@@ -62,13 +62,17 @@ namespace MipsISA
             switch(width)
             {
               case SingleWidth:
-                void *float_ptr = &regs[floatReg];
-                return *(float *) float_ptr;
+                {
+                    void *float_ptr = &regs[floatReg];
+                    return *(float *) float_ptr;
+                }
 
               case DoubleWidth:
-                uint64_t double_val = (FloatReg64)regs[floatReg + 1] << 32 | regs[floatReg];
-                void *double_ptr = &double_val;
-                return *(double *) double_ptr;
+                {
+                    uint64_t double_val = (FloatReg64)regs[floatReg + 1] << 32 | regs[floatReg];
+                    void *double_ptr = &double_val;
+                    return *(double *) double_ptr;
+                }
 
               default:
                 panic("Attempted to read a %d bit floating point register!", width);
@@ -99,21 +103,24 @@ namespace MipsISA
 
         Fault setReg(int floatReg, const FloatReg &val, int width)
         {
-
             switch(width)
             {
               case SingleWidth:
-                float temp = val;
-                void *float_ptr = &temp;
-                regs[floatReg] = *(FloatReg32 *) float_ptr;
-                break;
+                {
+                    float temp = val;
+                    void *float_ptr = &temp;
+                    regs[floatReg] = *(FloatReg32 *) float_ptr;
+                    break;
+                }
 
               case DoubleWidth:
-                const void *double_ptr = &val;
-                FloatReg64 temp_double = *(FloatReg64 *) double_ptr;
-                regs[floatReg + 1] = temp_double >> 32;
-                regs[floatReg] = temp_double;
-                break;
+                {
+                    const void *double_ptr = &val;
+                    FloatReg64 temp_double = *(FloatReg64 *) double_ptr;
+                    regs[floatReg + 1] = temp_double >> 32;
+                    regs[floatReg] = 0x0000FFFF & temp_double;
+                    break;
+                }
 
               default:
                 panic("Attempted to read a %d bit floating point register!", width);
@@ -148,14 +155,6 @@ namespace MipsISA
         void unserialize(Checkpoint *cp, const std::string &section);
     };
 
-    enum MiscFloatRegNums {
-       FIR = NumFloatArchRegs,
-       FCCR,
-       FEXR,
-       FENR,
-       FCSR
-    };
-
 } // namespace MipsISA
 
 #endif
-- 
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