From 753adb38d5471d23315d1bcfc6a744d1c6e03975 Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Fri, 22 Jun 2007 19:03:42 -0400 Subject: mips import pt. 1 src/arch/mips/SConscript: "mips import pt.1". --HG-- extra : convert_revision : 2e393341938bebf32fb638a209262d074fad4cc1 --- src/arch/mips/regfile/float_regfile.hh | 15 +- src/arch/mips/regfile/int_regfile.hh | 24 ++- src/arch/mips/regfile/misc_regfile.cc | 377 +++++++++++++++++++++++++++++++++ src/arch/mips/regfile/misc_regfile.hh | 273 ++++++++---------------- src/arch/mips/regfile/regfile.hh | 65 +++--- 5 files changed, 537 insertions(+), 217 deletions(-) create mode 100755 src/arch/mips/regfile/misc_regfile.cc (limited to 'src/arch/mips/regfile') diff --git a/src/arch/mips/regfile/float_regfile.hh b/src/arch/mips/regfile/float_regfile.hh index ce5f1fdde..21c16c238 100644 --- a/src/arch/mips/regfile/float_regfile.hh +++ b/src/arch/mips/regfile/float_regfile.hh @@ -88,12 +88,9 @@ namespace MipsISA public: - void clear() - { - bzero(regs, sizeof(regs)); - } + void clear() { bzero(®s, sizeof(regs)); } - double readReg(int floatReg, int width) + double readReg(int floatReg, int width, unsigned tid = 0) { switch(width) { @@ -115,7 +112,7 @@ namespace MipsISA } } - FloatRegBits readRegBits(int floatReg, int width) + FloatRegBits readRegBits(int floatReg, int width, unsigned tid = 0) { if (floatReg < NumFloatArchRegs - 1) { switch(width) @@ -137,8 +134,9 @@ namespace MipsISA } } - Fault setReg(int floatReg, const FloatRegVal &val, int width) + Fault setReg(int floatReg, const FloatRegVal &val, int width, unsigned tid = 0) { + using namespace std; switch(width) { case SingleWidth: @@ -165,8 +163,9 @@ namespace MipsISA return NoFault; } - Fault setRegBits(int floatReg, const FloatRegBits &val, int width) + Fault setRegBits(int floatReg, const FloatRegBits &val, int width, unsigned tid = 0) { + using namespace std; switch(width) { diff --git a/src/arch/mips/regfile/int_regfile.hh b/src/arch/mips/regfile/int_regfile.hh index a45a17a85..2a034ad8d 100644 --- a/src/arch/mips/regfile/int_regfile.hh +++ b/src/arch/mips/regfile/int_regfile.hh @@ -47,8 +47,21 @@ namespace MipsISA } enum MiscIntRegNums { - HI = NumIntArchRegs, - LO + LO = NumIntArchRegs, + HI, + DSPACX0, + DSPLo1, + DSPHi1, + DSPACX1, + DSPLo2, + DSPHi2, + DSPACX2, + DSPLo3, + DSPHi3, + DSPACX3, + DSPControl, + DSPLo0 = LO, + DSPHi0 = HI }; class IntRegFile @@ -57,6 +70,8 @@ namespace MipsISA IntReg regs[NumIntRegs]; public: + void clear() { bzero(®s, sizeof(regs)); } + IntReg readReg(int intReg) { return regs[intReg]; @@ -64,7 +79,10 @@ namespace MipsISA Fault setReg(int intReg, const IntReg &val) { - regs[intReg] = val; + if (intReg != ZeroReg) { + regs[intReg] = val; + } + return NoFault; } diff --git a/src/arch/mips/regfile/misc_regfile.cc b/src/arch/mips/regfile/misc_regfile.cc new file mode 100755 index 000000000..c97d93cf9 --- /dev/null +++ b/src/arch/mips/regfile/misc_regfile.cc @@ -0,0 +1,377 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Korey Sewell + */ + +#include "base/bitfield.hh" + +#include "arch/mips/regfile/misc_regfile.hh" +#include "arch/mips/mt_constants.hh" +#include "arch/mips/faults.hh" + +#include "cpu/thread_context.hh" +#include "cpu/base.hh" +#include "cpu/exetrace.hh" +//#include "cpu/mixie/cpu.hh" + +using namespace std; + +std::string MiscRegFile::miscRegNames[NumMiscRegs] = +{"Index", "MVPControl", "MVPConf0", "MVPConf1", "", "", "", "", + "Random", "VPEControl", "VPEConf0", "VPEConf1", "YQMask", "VPESchedule", "VPEScheFBack", "VPEOpt", + "EntryLo0", "TCStatus", "TCBind", "TCRestart", "TCHalt", "TCContext", "TCSchedule", "TCScheFBack", + "EntryLo1", "", "", "", "", "", "", "", + "Context", "ContextConfig", "", "", "", "", "", "", + "PageMask", "PageGrain", "", "", "", "", "", "", + "Wired", "SRSConf0", "SRCConf1", "SRSConf2", "SRSConf3", "SRSConf4", "", "", + "HWREna", "", "", "", "", "", "", "", + "BadVAddr", "", "", "", "", "", "", "", + "Count", "", "", "", "", "", "", "", + "EntryHi", "", "", "", "", "", "", "", + "Compare", "", "", "", "", "", "", "", + "Status", "IntCtl", "SRSCtl", "SRSMap", "", "", "", "", + "Cause", "", "", "", "", "", "", "", + "EPC", "", "", "", "", "", "", "", + "PRId", "EBase", "", "", "", "", "", "", + "Config", "Config1", "Config2", "Config3", "", "", "", "", + "LLAddr", "", "", "", "", "", "", "", + "WatchLo0", "WatchLo1", "WatchLo2", "WatchLo3", "WatchLo4", "WatchLo5", "WatchLo6", "WatchLo7", + "WatchHi0", "WatchHi1", "WatchHi2", "WatchHi3", "WatchHi4", "WatchHi5", "WatchHi6", "WatchHi7", + "XCContext64", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "Debug", "TraceControl1", "TraceControl2", "UserTraceData", "TraceBPC", "", "", "", + "DEPC", "", "", "", "", "", "", "", + "PerfCnt0", "PerfCnt1", "PerfCnt2", "PerfCnt3", "PerfCnt4", "PerfCnt5", "PerfCnt6", "PerfCnt7", + "ErrCtl", "", "", "", "", "", "", "", + "CacheErr0", "CacheErr1", "CacheErr2", "CacheErr3", "", "", "", "", + "TagLo0", "DataLo1", "TagLo2", "DataLo3", "TagLo4", "DataLo5", "TagLo6", "DataLo7", + "TagHi0", "DataHi1", "TagHi2", "DataHi3", "TagHi4", "DataHi5", "TagHi6", "DataHi7", + "ErrorEPC", "", "", "", "", "", "", "", + "DESAVE", "", "", "", "", "", "", "", + "LLFlag" +}; + +MiscRegFile::MiscRegFile() +{ + init(); +} + +MiscRegFile::MiscRegFile(BaseCPU *_cpu) +{ + cpu = _cpu; + init(); +} + +void +MiscRegFile::init() +{ + miscRegFile.resize(NumMiscRegs); + bankType.resize(NumMiscRegs); + + for (int i=0; i < NumMiscRegs; i++) { + miscRegFile[i].resize(1); + bankType[i] = perProcessor; + } + + clear(0); +} + +void +MiscRegFile::clear(unsigned tid_or_vpn) +{ + for(int i = 0; i < NumMiscRegs; i++) { + miscRegFile[i][tid_or_vpn] = 0; + } +} + +void +MiscRegFile::expandForMultithreading(unsigned num_threads, unsigned num_vpes) +{ + // Initialize all Per-VPE regs + uint32_t per_vpe_regs[] = { VPEControl, VPEConf0, VPEConf1, YQMask, + VPESchedule, VPEScheFBack, VPEOpt, SRSConf0, + SRSConf1, SRSConf2, SRSConf3, SRSConf4, + EBase + }; + uint32_t num_vpe_regs = sizeof(per_vpe_regs) / 4; + for (int i = 0; i < num_vpe_regs; i++) { + if (num_vpes > 1) { + miscRegFile[per_vpe_regs[i]].resize(num_vpes); + } + bankType[per_vpe_regs[i]] = perVirtProcessor; + } + + // Initialize all Per-TC regs + uint32_t per_tc_regs[] = { Status, TCStatus, TCBind, TCRestart, TCHalt, + TCContext, TCSchedule, TCScheFBack, Debug, + LLAddr + }; + uint32_t num_tc_regs = sizeof(per_tc_regs) / 4; + + for (int i = 0; i < num_tc_regs; i++) { + miscRegFile[per_tc_regs[i]].resize(num_threads); + bankType[per_tc_regs[i]] = perThreadContext; + } + + + if (num_vpes > 1) { + for (int i=1; i < num_vpes; i++) { + clear(i); + } + } + +} + +//@TODO: Use MIPS STYLE CONSTANTS (e.g. TCHALT_H instead of TCH_H) +void +MiscRegFile::reset(std::string core_name, unsigned num_threads, + unsigned num_vpes) +{ + DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n", + num_threads, num_vpes); + + // Do Default CP0 initialization HERE + + // Do Initialization for MT cores here (eventually use + // core_name parameter to toggle this initialization) + // =================================================== + // Config + MiscReg cfg = readRegNoEffect(Config); + replaceBits(cfg, CFG_M, 1); + setRegNoEffect(Config, cfg); + + // Config1 + MiscReg cfg1 = readRegNoEffect(Config1); + replaceBits(cfg1, CFG1_M, 1); + setRegNoEffect(Config1, cfg1); + + // Config2 + MiscReg cfg2 = readRegNoEffect(Config2); + replaceBits(cfg2, CFG2_M, 1); + setRegNoEffect(Config2, cfg2); + + // Config3 + MiscReg cfg3 = readRegNoEffect(Config3); + replaceBits(cfg3, CFG3_MT, 1); + setRegNoEffect(Config3, cfg3); + + // MVPConf0 + MiscReg mvp_conf0 = readRegNoEffect(MVPConf0); + replaceBits(mvp_conf0, MVPC0_TCA, 1); + replaceBits(mvp_conf0, MVPC0_PVPE_HI, MVPC0_PVPE_LO, num_vpes - 1); + replaceBits(mvp_conf0, MVPC0_PTC_HI, MVPC0_PTC_LO, num_threads - 1); + setRegNoEffect(MVPConf0, mvp_conf0); + + // VPEConf0 + MiscReg vpe_conf0 = readRegNoEffect(VPEConf0); + replaceBits(vpe_conf0, VPEC0_MVP, 1); + setRegNoEffect(VPEConf0, vpe_conf0); + + // TCBind + for (int tid = 0; tid < num_threads; tid++) { + MiscReg tc_bind = readRegNoEffect(TCBind, tid); + replaceBits(tc_bind, TCB_CUR_TC_HI, TCB_CUR_TC_LO, tid); + setRegNoEffect(TCBind, tc_bind, tid); + } + + // TCHalt + MiscReg tc_halt = readRegNoEffect(TCHalt); + replaceBits(tc_halt, TCH_H, 0); + setRegNoEffect(TCHalt, tc_halt); + /*for (int tid = 1; tid < num_threads; tid++) { + // Set TCHalt Halt bit to 1 for all other threads + tc_halt = readRegNoEffect(TCHalt, tid); + replaceBits(tc_halt, TCH_H, 1); + setReg(TCHalt, tc_halt, tid); + }*/ + + // TCStatus + // Set TCStatus Activated to 1 for the initial thread that is running + MiscReg tc_status = readRegNoEffect(TCStatus); + replaceBits(tc_status, TCS_A, 1); + setRegNoEffect(TCStatus, tc_status); + + // Set Dynamically Allocatable bit to 1 for all other threads + for (int tid = 0; tid < num_threads; tid++) { + tc_status = readRegNoEffect(TCStatus, tid); + replaceBits(tc_status, TCSTATUS_DA, 1); + setRegNoEffect(TCStatus, tc_status, tid); + } +} + +inline std::string +MipsISA::getMiscRegName(unsigned reg_idx) +{ + return MiscRegFile::miscRegNames[reg_idx]; +} + +inline unsigned +MiscRegFile::getVPENum(unsigned tid) +{ + unsigned tc_bind = miscRegFile[TCBind][tid]; + return bits(tc_bind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO); +} + +MiscReg +MiscRegFile::readRegNoEffect(int misc_reg, unsigned tid) +{ + unsigned reg_sel = (bankType[misc_reg] == perThreadContext) + ? tid : getVPENum(tid); + + return miscRegFile[misc_reg][reg_sel]; +} + +//@TODO: MIPS MT's register view automatically connects +// Status to TCStatus depending on current thread +MiscReg +MiscRegFile::readReg(int misc_reg, + ThreadContext *tc, unsigned tid) +{ + DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) with effect.\n", + misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg)); + + unsigned reg_sel = (bankType[misc_reg] == perThreadContext) + ? tid : getVPENum(tid); + + switch (misc_reg) + { + default: + return miscRegFile[misc_reg][reg_sel]; + } +} + +void +MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid) +{ + unsigned reg_sel = (bankType[misc_reg] == perThreadContext) + ? tid : getVPENum(tid); + + miscRegFile[misc_reg][reg_sel] = val; +} + +// PROGRAMMER'S NOTES: +// (1) Some CP0 Registers have fields that cannot +// be overwritten. Make sure to handle those particular registers +// with care! +void +MiscRegFile::setReg(int misc_reg, const MiscReg &val, + ThreadContext *tc, unsigned tid) +{ + unsigned reg_sel = (bankType[misc_reg] == perThreadContext) + ? tid : getVPENum(tid); + + DPRINTF(MipsPRA, "[tid:%i]: Setting CP0 Register:%u Select:%u (%s) to %#x, with effect.\n", + tid, misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg), val); + + MiscReg cp0_val = filterCP0Write(misc_reg, val); + + miscRegFile[misc_reg][reg_sel] = cp0_val; + + scheduleCP0Update(); +} + +void +MiscRegFile::scheduleCP0Update(int delay) +{ + if (!cp0Updated) { + cp0Updated = true; + + //schedule UPDATE + CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0); + cp0_event->schedule(curTick + cpu->cycles(delay)); + } +} + +void +MiscRegFile::updateCPU() +{ + /////////////////////////////////////////////////////////////////// + // + // EVALUATE CP0 STATE FOR MIPS MT + // + /////////////////////////////////////////////////////////////////// + unsigned mvp_conf0 = readRegNoEffect(MVPConf0); + unsigned num_threads = bits(mvp_conf0, MVPC0_PTC_HI, MVPC0_PTC_LO) + 1; + + for (int tid = 0; tid < num_threads; tid++) { + MiscReg tc_status = readRegNoEffect(TCStatus, tid); + MiscReg tc_halt = readRegNoEffect(TCHalt, tid); + + //@todo: add vpe/mt check here thru mvpcontrol & vpecontrol regs + if (bits(tc_halt, TCH_H) == 1 || bits(tc_status, TCS_A) == 0) { + haltThread(cpu->getContext(tid)); + } else if (bits(tc_halt, TCH_H) == 0 && bits(tc_status, TCS_A) == 1) { + restoreThread(cpu->getContext(tid)); + } + } + + num_threads = bits(mvp_conf0, MVPC0_PTC_HI, MVPC0_PTC_LO) + 1; + + // Toggle update flag after we finished updating + cp0Updated = false; +} + +MiscRegFile::CP0Event::CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type) + : Event(&mainEventQueue, CPU_Tick_Pri), cp0(_cp0), cpu(_cpu), cp0EventType(e_type) +{ } + +void +MiscRegFile::CP0Event::process() +{ + switch (cp0EventType) + { + case UpdateCP0: + cp0->updateCPU(); + break; + } + + //cp0EventRemoveList.push(this); +} + +const char * +MiscRegFile::CP0Event::description() +{ + return "Coprocessor-0 event"; +} + +void +MiscRegFile::CP0Event::scheduleEvent(int delay) +{ + if (squashed()) + reschedule(curTick + cpu->cycles(delay)); + else if (!scheduled()) + schedule(curTick + cpu->cycles(delay)); +} + +void +MiscRegFile::CP0Event::unscheduleEvent() +{ + if (scheduled()) + squash(); +} diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh index 53ee09512..54b086a8b 100644 --- a/src/arch/mips/regfile/misc_regfile.hh +++ b/src/arch/mips/regfile/misc_regfile.hh @@ -31,213 +31,128 @@ #ifndef __ARCH_MIPS_REGFILE_MISC_REGFILE_HH__ #define __ARCH_MIPS_REGFILE_MISC_REGFILE_HH__ +#include "arch/mips/isa_traits.hh" #include "arch/mips/types.hh" +#include "arch/mips/mt.hh" +#include "arch/mips/mt_constants.hh" +#include "base/bitfield.hh" +#include "cpu/base.hh" #include "sim/faults.hh" +#include class ThreadContext; namespace MipsISA { - static inline std::string getMiscRegName(RegIndex) - { - return ""; - } - - //Coprocessor 0 Register Names - enum MiscRegTags { - //Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8 - //(Register Number-Register Select) Summary of Register - //------------------------------------------------------ - Index = 0, //Bank 0: 0 - 3 - MVPControl, - MVPConf0, - MVPConf1, - - Random = 8, //Bank 1: 8 - 15 - VPEControl, - VPEConf0, - VPEConf1, - YQMask, - VPESchedule, - VPEScheFBack, - VPEOpt, - - EntryLo0 = 16, //Bank 2: 16 - 23 - TCStatus, - TCBind, - TCRestart, - TCHalt, - TCContext, - TCSchedule, - TCScheFBack, - - EntryLo1 = 24, // Bank 3: 24 - - Context = 32, // Bank 4: 32 - 33 - ContextConfig, - - //PageMask = 40, //Bank 5: 40 - 41 - PageGrain = 41, - - Wired = 48, //Bank 6: 48 - 55 - SRSConf0, - SRSConf1, - SRSConf2, - SRSConf3, - SRSConf4, - - HWRena = 56, //Bank 7: 56 - - BadVAddr = 63, //Bank 8: 63 - - Count = 64, //Bank 9: 64 - - EntryHi = 72, //Bank 10:72 - 79 - - Compare = 80, //Bank 10:80 - 87 - - Status = 88, //Bank 12:88 - 96 - IntCtl = 89, - SRSCtl = 90, - SRSMap = 91, - - Cause = 97, //97-104 - - EPC = 105, //105-112 - - PRId = 113, //113-120, - EBase = 114, - - Config = 121, //Bank 16: 121-128 - Config1 = 122, - Config2 = 123, - Config3 = 124, - Config6 = 127, - Config7 = 128, - - - LLAddr = 129, //Bank 17: 129-136 - - WatchLo0 = 137, //Bank 18: 137-144 - WatchLo1 = 138, - WatchLo2 = 139, - WatchLo3 = 140, - WatchLo4 = 141, - WatchLo5 = 142, - WatchLo6 = 143, - WatchLo7 = 144, - - WatchHi0 = 145,//Bank 19: 145-152 - WatchHi1 = 146, - WatchHi2 = 147, - WatchHi3 = 148, - WatchHi4 = 149, - WatchHi5 = 150, - WatchHi6 = 151, - WatchHi7 = 152, - - XCContext64 = 153, //Bank 20: 153-160 - - //Bank 21: 161-168 - - //Bank 22: 169-176 - - Debug = 177, //Bank 23: 177-184 - TraceControl1 = 178, - TraceControl2 = 179, - UserTraceData = 180, - TraceBPC = 181, - - DEPC = 185,//Bank 24: 185-192 - - PerfCnt0 = 193,//Bank 25: 193 - 200 - PerfCnt1 = 194, - PerfCnt2 = 195, - PerfCnt3 = 196, - PerfCnt4 = 197, - PerfCnt5 = 198, - PerfCnt6 = 199, - PerfCnt7 = 200, + class MiscRegFile { + public: + // Give RegFile object, private access + friend class RegFile; - ErrCtl = 201, //Bank 26: 201 - 208 + // The MIPS name for this file is CP0 or Coprocessor 0 + typedef MiscRegFile CP0; - CacheErr0 = 209, //Bank 27: 209 - 216 - CacheErr1 = 210, - CacheErr2 = 211, - CacheErr3 = 212, + protected: + enum BankType { + perProcessor, + perThreadContext, + perVirtProcessor + }; - TagLo0 = 217,//Bank 28: 217 - 224 - DataLo1 = 218, - TagLo2 = 219, - DataLo3 = 220, - TagLo4 = 221, - DataLo5 = 222, - TagLo6 = 223, - DataLo7 = 234, + std::vector > miscRegFile; + std::vector bankType; - TagHi0 = 233,//Bank 29: 233 - 240 - DataHi1 = 234, - TagHi2 = 235, - DataHi3 = 236, - TagHi4 = 237, - DataHi5 = 238, - TagHi6 = 239, - DataHi7 = 240, + BaseCPU *cpu; + public: + MiscRegFile(); + MiscRegFile(BaseCPU *cpu); - ErrorEPC = 249,//Bank 30: 241 - 248 + void init(); - DESAVE = 257//Bank 31: 249-256 - }; + void clear(unsigned tid_or_vpn = 0); - class MiscRegFile { + void reset(std::string core_name, unsigned num_threads, unsigned num_vpes); - protected: - uint64_t fpcr; // floating point condition codes - // FPCR is not used in MIPS. Condition - // codes are kept as part of the FloatRegFile + void expandForMultithreading(unsigned num_threads, unsigned num_vpes); - bool lock_flag; // lock flag for LL/SC - // use LL reg. in the future + void copyMiscRegs(ThreadContext *tc); - Addr lock_addr; // lock address for LL/SC - // use LLAddr reg. in the future + inline unsigned getVPENum(unsigned tid); + + ////////////////////////////////////////////////////////// + // + // READ/WRITE CP0 STATE + // + // + ////////////////////////////////////////////////////////// + //@TODO: MIPS MT's register view automatically connects + // Status to TCStatus depending on current thread + void updateCP0ReadView(int misc_reg, unsigned tid) { } + MiscReg readRegNoEffect(int misc_reg, unsigned tid = 0); + MiscReg readReg(int misc_reg, + ThreadContext *tc, unsigned tid = 0); + + MiscReg filterCP0Write(int misc_reg, MiscReg val) { return val; } + void setRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0); + void setReg(int misc_reg, const MiscReg &val, + ThreadContext *tc, unsigned tid = 0); - MiscReg miscRegFile[NumMiscRegs]; + ////////////////////////////////////////////////////////// + // + // DECLARE INTERFACE THAT WILL ALLOW A MiscRegFile (Cop0) + // TO SCHEDULE EVENTS + // + ////////////////////////////////////////////////////////// - public: - void clear() - { - fpcr = 0; - lock_flag = 0; - lock_addr = 0; - } + // Flag that is set when CP0 state has been written to. + bool cp0Updated; - void copyMiscRegs(ThreadContext *tc); + // Enumerated List of CP0 Event Types + enum CP0EventType { + UpdateCP0 + }; - MiscReg readRegNoEffect(int misc_reg) + // Declare A CP0Event Class for scheduling + class CP0Event : public Event { - return miscRegFile[misc_reg]; - } + protected: + MiscRegFile::CP0 *cp0; + BaseCPU *cpu; + CP0EventType cp0EventType; + Fault fault; - MiscReg readReg(int misc_reg, ThreadContext *tc) - { - return miscRegFile[misc_reg]; - } + public: + /** Constructs a CP0 event. */ + CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type); - void setRegNoEffect(int misc_reg, const MiscReg &val) - { - miscRegFile[misc_reg] = val; - } + /** Process this event. */ + virtual void process(); - void setReg(int misc_reg, const MiscReg &val, - ThreadContext *tc) - { - miscRegFile[misc_reg] = val; - } + /** Returns the description of this event. */ + const char *description(); - friend class RegFile; + /** Schedule This Event */ + void scheduleEvent(int delay); + + /** Unschedule This Event */ + void unscheduleEvent(); + }; + + // Schedule a CP0 Update Event + void scheduleCP0Update(int delay = 0); + + // If any changes have been made, then check the state for changes + // and if necessary alert the CPU + void updateCPU(); + + // Keep a List of CPU Events that need to be deallocated + std::queue cp0EventRemoveList; + + static std::string miscRegNames[NumMiscRegs]; }; + + inline std::string getMiscRegName(unsigned reg_idx); } // namespace MipsISA #endif diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh index 387fbd5c8..f13653132 100644 --- a/src/arch/mips/regfile/regfile.hh +++ b/src/arch/mips/regfile/regfile.hh @@ -32,6 +32,8 @@ #define __ARCH_MIPS_REGFILE_REGFILE_HH__ #include "arch/mips/types.hh" +#include "arch/mips/isa_traits.hh" +#include "arch/mips/mt.hh" #include "arch/mips/regfile/int_regfile.hh" #include "arch/mips/regfile/float_regfile.hh" #include "arch/mips/regfile/misc_regfile.hh" @@ -49,33 +51,50 @@ namespace MipsISA MiscRegFile miscRegFile; // control register file public: - void clear() + { + intRegFile.clear(); + floatRegFile.clear(); + miscRegFile.clear(); + } + + void reset(std::string core_name, unsigned num_threads, unsigned num_vpes) { bzero(&intRegFile, sizeof(intRegFile)); bzero(&floatRegFile, sizeof(floatRegFile)); - bzero(&miscRegFile, sizeof(miscRegFile)); + miscRegFile.reset(core_name, num_threads, num_vpes); + } + + IntReg readIntReg(int intReg) + { + return intRegFile.readReg(intReg); + } + + Fault setIntReg(int intReg, const IntReg &val) + { + return intRegFile.setReg(intReg, val); } - MiscReg readMiscRegNoEffect(int miscReg) + MiscReg readMiscRegNoEffect(int miscReg, unsigned tid = 0) { - return miscRegFile.readRegNoEffect(miscReg); + return miscRegFile.readRegNoEffect(miscReg, tid); } - MiscReg readMiscReg(int miscReg, ThreadContext *tc) + MiscReg readMiscReg(int miscReg, ThreadContext *tc, + unsigned tid = 0) { - return miscRegFile.readReg(miscReg, tc); + return miscRegFile.readReg(miscReg, tc, tid); } - void setMiscRegNoEffect(int miscReg, const MiscReg &val) + void setMiscRegNoEffect(int miscReg, const MiscReg &val, unsigned tid = 0) { - miscRegFile.setRegNoEffect(miscReg, val); + miscRegFile.setRegNoEffect(miscReg, val, tid); } void setMiscReg(int miscReg, const MiscReg &val, - ThreadContext * tc) + ThreadContext * tc, unsigned tid = 0) { - miscRegFile.setReg(miscReg, val, tc); + miscRegFile.setReg(miscReg, val, tc, tid); } FloatRegVal readFloatReg(int floatReg) @@ -98,35 +117,26 @@ namespace MipsISA return floatRegFile.readRegBits(floatReg,width); } - void setFloatReg(int floatReg, const FloatRegVal &val) - { - floatRegFile.setReg(floatReg, val, SingleWidth); - } - - void setFloatReg(int floatReg, const FloatRegVal &val, int width) + Fault setFloatReg(int floatReg, const FloatRegVal &val) { - floatRegFile.setReg(floatReg, val, width); + return floatRegFile.setReg(floatReg, val, SingleWidth); } - void setFloatRegBits(int floatReg, const FloatRegBits &val) + Fault setFloatReg(int floatReg, const FloatRegVal &val, int width) { - floatRegFile.setRegBits(floatReg, val, SingleWidth); + return floatRegFile.setReg(floatReg, val, width); } - void setFloatRegBits(int floatReg, const FloatRegBits &val, int width) + Fault setFloatRegBits(int floatReg, const FloatRegBits &val) { - floatRegFile.setRegBits(floatReg, val, width); + return floatRegFile.setRegBits(floatReg, val, SingleWidth); } - IntReg readIntReg(int intReg) + Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width) { - return intRegFile.readReg(intReg); + return floatRegFile.setRegBits(floatReg, val, width); } - void setIntReg(int intReg, const IntReg &val) - { - intRegFile.setReg(intReg, val); - } protected: Addr pc; // program counter @@ -134,6 +144,7 @@ namespace MipsISA Addr nnpc; // next-next-cycle program counter // used to implement branch delay slot // not real register + public: Addr readPC() { -- cgit v1.2.3