From 800e6ecc07d01c49808cc4f9597d94cc8cfd9fae Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 11 Aug 2006 19:43:10 -0400 Subject: Pushed most of constants.hh back into isa_traits.hh and regfile.hh and created a seperate file for the syscallreturn class. --HG-- extra : convert_revision : 9507ea1c09fda959f00aec9ec8ffb887ec8dd0f9 --- src/arch/mips/regfile/float_regfile.hh | 48 ++++++++-- src/arch/mips/regfile/int_regfile.hh | 12 ++- src/arch/mips/regfile/misc_regfile.hh | 155 +++++++++++++++++++++++++++++++-- src/arch/mips/regfile/regfile.hh | 11 +-- 4 files changed, 202 insertions(+), 24 deletions(-) (limited to 'src/arch/mips/regfile') diff --git a/src/arch/mips/regfile/float_regfile.hh b/src/arch/mips/regfile/float_regfile.hh index 61efbb416..f057461ae 100644 --- a/src/arch/mips/regfile/float_regfile.hh +++ b/src/arch/mips/regfile/float_regfile.hh @@ -26,24 +26,56 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __ARCH_MIPS_FLOAT_REGFILE_HH__ -#define __ARCH_MIPS_FLOAT_REGFILE_HH__ +#ifndef __ARCH_MIPS_REGFILE_FLOAT_REGFILE_HH__ +#define __ARCH_MIPS_REGFILE_FLOAT_REGFILE_HH__ #include "arch/mips/types.hh" -#include "arch/mips/constants.hh" +#include "arch/mips/isa_traits.hh" #include "base/misc.hh" #include "base/bitfield.hh" -#include "config/full_system.hh" -#include "sim/byteswap.hh" #include "sim/faults.hh" -#include "sim/host.hh" + +#include class Checkpoint; -class ExecContext; -class Regfile; namespace MipsISA { + const uint32_t MIPS32_QNAN = 0x7fbfffff; + const uint64_t MIPS64_QNAN = ULL(0x7fbfffffffffffff); + + enum FPControlRegNums { + FIR = NumFloatArchRegs, + FCCR, + FEXR, + FENR, + FCSR + }; + + enum FCSRBits { + Inexact = 1, + Underflow, + Overflow, + DivideByZero, + Invalid, + Unimplemented + }; + + enum FCSRFields { + Flag_Field = 1, + Enable_Field = 6, + Cause_Field = 11 + }; + + const int SingleWidth = 32; + const int SingleBytes = SingleWidth / 4; + + const int DoubleWidth = 64; + const int DoubleBytes = DoubleWidth / 4; + + const int QuadWidth = 128; + const int QuadBytes = QuadWidth / 4; + class FloatRegFile { protected: diff --git a/src/arch/mips/regfile/int_regfile.hh b/src/arch/mips/regfile/int_regfile.hh index 5add1b7be..5496fc1f5 100644 --- a/src/arch/mips/regfile/int_regfile.hh +++ b/src/arch/mips/regfile/int_regfile.hh @@ -28,20 +28,24 @@ * Authors: Korey Sewell */ -#ifndef __ARCH_MIPS_INT_REGFILE_HH__ -#define __ARCH_MIPS_INT_REGFILE_HH__ +#ifndef __ARCH_MIPS_REGFILE_INT_REGFILE_HH__ +#define __ARCH_MIPS_REGFILE_INT_REGFILE_HH__ #include "arch/mips/types.hh" -#include "arch/mips/constants.hh" +#include "arch/mips/isa_traits.hh" #include "base/misc.hh" #include "sim/faults.hh" class Checkpoint; class ThreadContext; -class Regfile; namespace MipsISA { + enum MiscIntRegNums { + HI = NumIntArchRegs, + LO + }; + class IntRegFile { protected: diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh index 67aef9c63..66d3218d4 100644 --- a/src/arch/mips/regfile/misc_regfile.hh +++ b/src/arch/mips/regfile/misc_regfile.hh @@ -28,19 +28,164 @@ * Authors: Korey Sewell */ -#ifndef __ARCH_MIPS_MISC_REGFILE_HH__ -#define __ARCH_MIPS_MISC_REGFILE_HH__ +#ifndef __ARCH_MIPS_REGFILE_MISC_REGFILE_HH__ +#define __ARCH_MIPS_REGFILE_MISC_REGFILE_HH__ +#include "arch/mips/isa_traits.hh" #include "arch/mips/types.hh" -#include "arch/mips/constants.hh" #include "sim/faults.hh" -class Checkpoint; class ThreadContext; -class Regfile; namespace MipsISA { + //Coprocessor 0 Register Names + enum MiscRegTags { + //Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8 + //(Register Number-Register Select) Summary of Register + //------------------------------------------------------ + Index = 0, //Bank 0: 0 - 3 + MVPControl, + MVPConf0, + MVPConf1, + + Random = 8, //Bank 1: 8 - 15 + VPEControl, + VPEConf0, + VPEConf1, + YQMask, + VPESchedule, + VPEScheFBack, + VPEOpt, + + EntryLo0 = 16, //Bank 2: 16 - 23 + TCStatus, + TCBind, + TCRestart, + TCHalt, + TCContext, + TCSchedule, + TCScheFBack, + + EntryLo1 = 24, // Bank 3: 24 + + Context = 32, // Bank 4: 32 - 33 + ContextConfig, + + //PageMask = 40, //Bank 5: 40 - 41 + PageGrain = 41, + + Wired = 48, //Bank 6: 48 - 55 + SRSConf0, + SRSConf1, + SRSConf2, + SRSConf3, + SRSConf4, + + HWRena = 56, //Bank 7: 56 + + BadVAddr = 63, //Bank 8: 63 + + Count = 64, //Bank 9: 64 + + EntryHi = 72, //Bank 10:72 - 79 + + Compare = 80, //Bank 10:80 - 87 + + Status = 88, //Bank 12:88 - 96 + IntCtl = 89, + SRSCtl = 90, + SRSMap = 91, + + Cause = 97, //97-104 + + EPC = 105, //105-112 + + PRId = 113, //113-120, + EBase = 114, + + Config = 121, //Bank 16: 121-128 + Config1 = 122, + Config2 = 123, + Config3 = 124, + Config6 = 127, + Config7 = 128, + + + LLAddr = 129, //Bank 17: 129-136 + + WatchLo0 = 137, //Bank 18: 137-144 + WatchLo1 = 138, + WatchLo2 = 139, + WatchLo3 = 140, + WatchLo4 = 141, + WatchLo5 = 142, + WatchLo6 = 143, + WatchLo7 = 144, + + WatchHi0 = 145,//Bank 19: 145-152 + WatchHi1 = 146, + WatchHi2 = 147, + WatchHi3 = 148, + WatchHi4 = 149, + WatchHi5 = 150, + WatchHi6 = 151, + WatchHi7 = 152, + + XCContext64 = 153, //Bank 20: 153-160 + + //Bank 21: 161-168 + + //Bank 22: 169-176 + + Debug = 177, //Bank 23: 177-184 + TraceControl1 = 178, + TraceControl2 = 179, + UserTraceData = 180, + TraceBPC = 181, + + DEPC = 185,//Bank 24: 185-192 + + PerfCnt0 = 193,//Bank 25: 193 - 200 + PerfCnt1 = 194, + PerfCnt2 = 195, + PerfCnt3 = 196, + PerfCnt4 = 197, + PerfCnt5 = 198, + PerfCnt6 = 199, + PerfCnt7 = 200, + + ErrCtl = 201, //Bank 26: 201 - 208 + + CacheErr0 = 209, //Bank 27: 209 - 216 + CacheErr1 = 210, + CacheErr2 = 211, + CacheErr3 = 212, + + TagLo0 = 217,//Bank 28: 217 - 224 + DataLo1 = 218, + TagLo2 = 219, + DataLo3 = 220, + TagLo4 = 221, + DataLo5 = 222, + TagLo6 = 223, + DataLo7 = 234, + + TagHi0 = 233,//Bank 29: 233 - 240 + DataHi1 = 234, + TagHi2 = 235, + DataHi3 = 236, + TagHi4 = 237, + DataHi5 = 238, + TagHi6 = 239, + DataHi7 = 240, + + + ErrorEPC = 249,//Bank 30: 241 - 248 + + DESAVE = 257//Bank 31: 249-256 + }; + class MiscRegFile { protected: diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh index a68120299..dce015a36 100644 --- a/src/arch/mips/regfile/regfile.hh +++ b/src/arch/mips/regfile/regfile.hh @@ -28,11 +28,11 @@ * Authors: Korey Sewell */ -#ifndef __ARCH_MIPS_REGFILE_HH__ -#define __ARCH_MIPS_REGFILE_HH__ +#ifndef __ARCH_MIPS_REGFILE_REGFILE_HH__ +#define __ARCH_MIPS_REGFILE_REGFILE_HH__ #include "arch/mips/types.hh" -#include "arch/mips/constants.hh" +#include "arch/mips/isa_traits.hh" #include "arch/mips/regfile/int_regfile.hh" #include "arch/mips/regfile/float_regfile.hh" #include "arch/mips/regfile/misc_regfile.hh" @@ -171,10 +171,7 @@ namespace MipsISA void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); - typedef int ContextParam; - typedef int ContextVal; - - void changeContext(ContextParam param, ContextVal val) + void changeContext(RegContextParam param, RegContextVal val) { } }; -- cgit v1.2.3