From 608641e23c7f2288810c3f23a1a63790b664f2ab Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Sun, 26 Jul 2015 10:21:20 -0500 Subject: cpu: implements vector registers This adds a vector register type. The type is defined as a std::array of a fixed number of uint64_ts. The isa_parser.py has been modified to parse vector register operands and generate the required code. Different cpus have vector register files now. --- src/arch/mips/registers.hh | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'src/arch/mips/registers.hh') diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh index 0ac84cc7f..e7d5e346c 100644 --- a/src/arch/mips/registers.hh +++ b/src/arch/mips/registers.hh @@ -55,6 +55,7 @@ const int MaxShadowRegSets = 16; // Maximum number of shadow register sets const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;// const int NumCCRegs = 0; +const int NumVectorRegs = 0; const uint32_t MIPS32_QNAN = 0x7fbfffff; const uint64_t MIPS64_QNAN = ULL(0x7ff7ffffffffffff); @@ -278,7 +279,8 @@ const int NumMiscRegs = MISCREG_NUMREGS; // These help enumerate all the registers for dependence tracking. const int FP_Reg_Base = NumIntRegs; const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs; -const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0 +const int Vector_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0 +const int Misc_Reg_Base = Vector_Reg_Base + NumVectorRegs; const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs; const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; @@ -297,6 +299,12 @@ typedef uint64_t MiscReg; // dummy typedef since we don't have CC regs typedef uint8_t CCReg; +// vector register file entry type +typedef uint64_t VectorRegElement; +const int NumVectorRegElements = 0; +const int VectorRegBytes = NumVectorRegElements * sizeof(VectorRegElement); +typedef std::array VectorReg; + typedef union { IntReg intreg; FloatReg fpreg; -- cgit v1.2.3