From 5f7879a9352985775abef9515e216591a2e3e39d Mon Sep 17 00:00:00 2001
From: Korey Sewell <ksewell@umich.edu>
Date: Wed, 14 Nov 2007 06:24:47 -0500
Subject: Get MIPS_SE actually working again by actually by fixing TLB stuff
 and running hello world

--HG--
extra : convert_revision : 0944e7661934baddca1f1a895af0b75be2d96b10
---
 src/arch/mips/tlb.cc | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

(limited to 'src/arch/mips/tlb.cc')

diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index 15f4b762b..526292603 100644
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -47,6 +47,8 @@
 #include "base/str.hh"
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
+#include "sim/process.hh"
+#include "mem/page_table.hh"
 #include "params/MipsDTB.hh"
 #include "params/MipsITB.hh"
 #include "params/MipsTLB.hh"
@@ -314,6 +316,15 @@ TLB::regStats()
 Fault
 ITB::translate(RequestPtr &req, ThreadContext *tc)
 {
+#if !FULL_SYSTEM
+    Process * p = tc->getProcessPtr();
+
+    Fault fault = p->pTable->translate(req);
+    if(fault != NoFault)
+        return fault;
+
+    return NoFault;
+#else
   if(MipsISA::IsKSeg0(req->getVaddr()))
     {
       // Address will not be translated through TLB, set response, and go!
@@ -416,11 +427,21 @@ ITB::translate(RequestPtr &req, ThreadContext *tc)
         }
     }
   return checkCacheability(req);
+#endif
 }
 
 Fault
 DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
 {
+#if !FULL_SYSTEM
+    Process * p = tc->getProcessPtr();
+
+    Fault fault = p->pTable->translate(req);
+    if(fault != NoFault)
+        return fault;
+
+    return NoFault;
+#else
   if(MipsISA::IsKSeg0(req->getVaddr()))
     {
       // Address will not be translated through TLB, set response, and go!
@@ -544,6 +565,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
         }
     }
     return checkCacheability(req);
+#endif
 }
 
 ///////////////////////////////////////////////////////////////////////
-- 
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