From 7b5a96f06b530db35637aca6f9d0f7a2ddfa6e60 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 8 Apr 2009 22:21:27 -0700
Subject: tlb: Don't separate the TLB classes into an instruction TLB and a
 data TLB

---
 src/arch/mips/tlb.hh | 32 ++++++--------------------------
 1 file changed, 6 insertions(+), 26 deletions(-)

(limited to 'src/arch/mips/tlb.hh')

diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index dc0babf9a..fa2ed3f85 100644
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -43,8 +43,7 @@
 #include "arch/mips/pagetable.hh"
 #include "base/statistics.hh"
 #include "mem/request.hh"
-#include "params/MipsDTB.hh"
-#include "params/MipsITB.hh"
+#include "params/MipsTLB.hh"
 #include "sim/faults.hh"
 #include "sim/tlb.hh"
 #include "sim/sim_object.hh"
@@ -138,34 +137,15 @@ class TLB : public BaseTLB
     void unserialize(Checkpoint *cp, const std::string &section);
 
     void regStats();
-};
-
-class ITB : public TLB {
-  public:
-    typedef MipsTLBParams Params;
-    ITB(const Params *p);
-
-    Fault translateAtomic(RequestPtr req, ThreadContext *tc);
-    void translateTiming(RequestPtr req, ThreadContext *tc,
-            Translation *translation);
-};
-
-class DTB : public TLB {
-  public:
-    typedef MipsTLBParams Params;
-    DTB(const Params *p);
 
     Fault translateAtomic(RequestPtr req, ThreadContext *tc,
-            bool write = false);
+            bool write=false, bool execute=false);
     void translateTiming(RequestPtr req, ThreadContext *tc,
-            Translation *translation, bool write = false);
-};
-
-class UTB : public ITB, public DTB {
-  public:
-    typedef MipsTLBParams Params;
-    UTB(const Params *p);
+            Translation *translation, bool write=false, bool execute=false);
 
+  private:
+    Fault translateInst(RequestPtr req, ThreadContext *tc);
+    Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
 };
 
 }
-- 
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