From 1f539f13c32ad5a9187d56a098d4c857639b0e05 Mon Sep 17 00:00:00 2001
From: Alexandru Dutu <alexandru.dutu@amd.com>
Date: Sun, 23 Nov 2014 18:01:09 -0800
Subject: mem: Page Table map api modification

This patch adds uncacheable/cacheable and read-only/read-write attributes to
the map method of PageTableBase. It also modifies the constructor of TlbEntry
structs for all architectures to consider the new attributes.
---
 src/arch/mips/pagetable.hh | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

(limited to 'src/arch/mips')

diff --git a/src/arch/mips/pagetable.hh b/src/arch/mips/pagetable.hh
index 8678eb7e4..992d6649b 100755
--- a/src/arch/mips/pagetable.hh
+++ b/src/arch/mips/pagetable.hh
@@ -83,7 +83,14 @@ struct TlbEntry
 {
     Addr _pageStart;
     TlbEntry() {}
-    TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
+    TlbEntry(Addr asn, Addr vaddr, Addr paddr,
+             bool uncacheable, bool read_only)
+        : _pageStart(paddr)
+    {
+        if (uncacheable || read_only)
+            warn("MIPS TlbEntry does not support uncacheable"
+                 " or read-only mappings\n");
+    }
 
     Addr pageStart()
     {
-- 
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