From 215041215b06f330d072b0537d7fe70739b4927d Mon Sep 17 00:00:00 2001
From: Korey Sewell <ksewell@umich.edu>
Date: Thu, 6 Jul 2006 11:25:44 -0400
Subject: more steps toward O3 SMT

src/arch/mips/isa/formats/fp.isa:
    Adjust for newmem
src/cpu/cpu_models.py:
    Use O3DynInst instead of convoluted way
src/cpu/o3/alpha/impl.hh:
    take out O3DynInst typedef here ...
src/cpu/o3/cpu.cc:
    open up the SMT functions in the O3CPU
src/cpu/static_inst.hh:
    Add O3DynInst
src/cpu/o3/dyn_inst.hh:
    Use to get ISA-specific O3DynInst

--HG--
extra : convert_revision : 3713187ead93e336e80889e23a1f1d2f36d664fe
---
 src/arch/mips/isa/formats/fp.isa | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

(limited to 'src/arch/mips')

diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa
index 1e5d62626..cdb892b3f 100644
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -142,10 +142,10 @@ output exec {{
                 cpu->setFloatRegBits(inst, 0, mips_nan, size);
 
                 //Read FCSR from FloatRegFile
-                uint32_t fcsr_bits = cpu->tc->readFloatRegBits(FCSR);
+                uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR);
 
                 //Write FCSR from FloatRegFile
-                cpu->tc->setFloatRegBits(FCSR, genInvalidVector(fcsr_bits));
+                cpu->tcBase()->setFloatRegBits(FCSR, genInvalidVector(fcsr_bits));
 
                 if (traceData) { traceData->setData(mips_nan); }
                 return true;
@@ -158,12 +158,12 @@ output exec {{
         fpResetCauseBits(%(CPU_exec_context)s *cpu)
         {
             //Read FCSR from FloatRegFile
-            uint32_t fcsr = cpu->tc->readFloatRegBits(FCSR);
+            uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FCSR);
 
             fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
 
             //Write FCSR from FloatRegFile
-            cpu->tc->setFloatRegBits(FCSR, fcsr);
+            cpu->tcBase()->setFloatRegBits(FCSR, fcsr);
         }
 }};
 
@@ -176,8 +176,9 @@ def template FloatingPointExecute {{
 
                 //When is the right time to reset cause bits?
                 //start of every instruction or every cycle?
+#if FULL_SYSTEM
                 fpResetCauseBits(xc);
-
+#endif
                 %(op_decl)s;
                 %(op_rd)s;
 
@@ -192,7 +193,10 @@ def template FloatingPointExecute {{
                     //----
                     //Check for IEEE 754 FP Exceptions
                     //fault = fpNanOperands((FPOp*)this, xc, Fd, traceData);
-                    if (!fpInvalidOp((FPOp*)this, xc, Fd, traceData) &&
+                    if (
+#if FULL_SYSTEM
+                        !fpInvalidOp((FPOp*)this, xc, Fd, traceData) &&
+#endif
                         fault == NoFault)
                     {
                         %(op_wb)s;
-- 
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