From 4d5f2c28a88f83d390e80407f55a8a02ead33878 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sat, 22 Oct 2011 22:30:07 -0700 Subject: syscall_emul: implement MAP_FIXED option to mmap() --- src/arch/mips/linux/linux.hh | 1 + 1 file changed, 1 insertion(+) (limited to 'src/arch/mips') diff --git a/src/arch/mips/linux/linux.hh b/src/arch/mips/linux/linux.hh index a2418cfb6..949cce8aa 100644 --- a/src/arch/mips/linux/linux.hh +++ b/src/arch/mips/linux/linux.hh @@ -65,6 +65,7 @@ class MipsLinux : public Linux /// For mmap(). static const unsigned TGT_MAP_ANONYMOUS = 0x800; + static const unsigned TGT_MAP_FIXED = 0x10; //@{ /// For getsysinfo(). -- cgit v1.2.3 From 6f9d294e8685f49d91af48065736ac1d67e53718 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sat, 22 Oct 2011 22:30:08 -0700 Subject: SE: move page allocation from PageTable to Process PageTable supported an allocate() call that called back through the Process to allocate memory, but did not have a method to map addresses without allocating new pages. It makes more sense for Process to do the allocation, so this method was renamed allocateMem() and moved to Process, and uses a new map() call on PageTable. The remaining uses of the process pointer in PageTable were only to get the name and the PID, so by passing these in directly in the constructor, we can make PageTable completely independent of Process. --- src/arch/mips/process.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/process.cc b/src/arch/mips/process.cc index c62b60b98..5643ff18a 100644 --- a/src/arch/mips/process.cc +++ b/src/arch/mips/process.cc @@ -136,7 +136,7 @@ MipsLiveProcess::argsInit(int pageSize) stack_min = roundDown(stack_min, pageSize); stack_size = stack_base - stack_min; // map memory - pTable->allocate(stack_min, roundUp(stack_size, pageSize)); + allocateMem(stack_min, roundUp(stack_size, pageSize)); // map out initial stack contents IntType argv_array_base = stack_min + intSize; // room for argc -- cgit v1.2.3 From d735abe5dabf483aafb0ccfb0a70cb7c3b0a5a74 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 31 Oct 2011 01:09:44 -0700 Subject: GCC: Get everything working with gcc 4.6.1. And by "everything" I mean all the quick regressions. --- src/arch/mips/isa/decoder.isa | 8 +++----- src/arch/mips/isa/formats/mt.isa | 22 ++++++---------------- src/arch/mips/isa/includes.isa | 2 ++ src/arch/mips/tlb.cc | 2 -- 4 files changed, 11 insertions(+), 23 deletions(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa index 7b8dafdba..179e409dd 100644 --- a/src/arch/mips/isa/decoder.isa +++ b/src/arch/mips/isa/decoder.isa @@ -497,8 +497,8 @@ decode OPCODE_HI default Unknown::unknown() { 0x2: mttc1({{ uint64_t data = xc->readRegOtherThread(RD + FP_Base_DepTag); - data = insertBits(data, top_bit, - bottom_bit, Rt); + data = insertBits(data, MT_H ? 63 : 31, + MT_H ? 32 : 0, Rt); xc->setRegOtherThread(RD + FP_Base_DepTag, data); }}); @@ -532,7 +532,7 @@ decode OPCODE_HI default Unknown::unknown() { panic("FP Control Value (%d) " "Not Available. Ignoring " "Access to Floating Control " - "Status Register", FS); + "S""tatus Register", FS); } xc->setRegOtherThread(FLOATREG_FCSR + FP_Base_DepTag, data); }}); @@ -776,7 +776,6 @@ decode OPCODE_HI default Unknown::unknown() { bits(pageGrain, pageGrain.esp) == 1) { SP = 1; } - IndexReg index = Index; Ptr->insertAt(newEntry, Index & 0x7FFFFFFF, SP); }}); 0x06: tlbwr({{ @@ -842,7 +841,6 @@ decode OPCODE_HI default Unknown::unknown() { bits(pageGrain, pageGrain.esp) == 1) { SP = 1; } - IndexReg index = Index; Ptr->insertAt(newEntry, Random, SP); }}); diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa index 1944d69d3..41f94e129 100644 --- a/src/arch/mips/isa/formats/mt.isa +++ b/src/arch/mips/isa/formats/mt.isa @@ -107,7 +107,7 @@ def template ThreadRegisterExecute {{ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; - int64_t data; + int64_t data M5_VAR_USED; %(op_decl)s; %(op_rd)s; @@ -126,17 +126,6 @@ def template ThreadRegisterExecute {{ } else if (vpeControl.targTC > mvpConf0.ptc) { data = -1; } else { - int top_bit = 0; - int bottom_bit = 0; - - if (MT_H == 1) { - top_bit = 63; - bottom_bit = 32; - } else { - top_bit = 31; - bottom_bit = 0; - } - %(code)s; } } else { @@ -203,10 +192,11 @@ def format MT_MFTR(code, *flags) {{ flags += ('IsNonSpeculative', ) # code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code - code += 'if (MT_H == 1) {\n' - code += 'data = bits(data, top_bit, bottom_bit);\n' - code += '}\n' - code += 'Rd = data;\n' + code += ''' + if (MT_H) + data = bits(data, 63, 32); + Rd = data; + ''' iop = InstObjParams(name, Name, 'MTOp', code, flags) header_output = BasicDeclare.subst(iop) diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa index c9f5da41d..4ce03b1c2 100644 --- a/src/arch/mips/isa/includes.isa +++ b/src/arch/mips/isa/includes.isa @@ -52,7 +52,9 @@ output decoder {{ #include "arch/mips/faults.hh" #include "arch/mips/isa_traits.hh" #include "arch/mips/mt_constants.hh" +#include "arch/mips/pagetable.hh" #include "arch/mips/pra_constants.hh" +#include "arch/mips/tlb.hh" #include "arch/mips/utility.hh" #include "base/loader/symtab.hh" #include "base/cprintf.hh" diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc index e35ac6d4a..57d8849e1 100644 --- a/src/arch/mips/tlb.cc +++ b/src/arch/mips/tlb.cc @@ -129,7 +129,6 @@ int TLB::probeEntry(Addr vpn, uint8_t asn) const { // assume not found... - PTE *retval = NULL; int Ind = -1; PageTable::const_iterator i = lookupTable.find(vpn); if (i != lookupTable.end()) { @@ -144,7 +143,6 @@ TLB::probeEntry(Addr vpn, uint8_t asn) const if (((vpn & InvMask) == (VPN & InvMask)) && (pte->G || (asn == pte->asid))) { // We have a VPN + ASID Match - retval = pte; Ind = index; break; } -- cgit v1.2.3