From 7846f59d0dcb36c13e06a3ba8a4c461e646582b6 Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Mon, 3 Jun 2013 13:55:41 +0200 Subject: arch: Create a method to finalize physical addresses in the TLB Some architectures (currently only x86) require some fixing-up of physical addresses after a normal address translation. This is usually to remap devices such as the APIC, but could be used for other memory mapped devices as well. When running the CPU in a using hardware virtualization, we still need to do these address fix-ups before inserting the request into the memory system. This patch moves this patch allows that code to be used by such CPUs without doing full address translations. --- src/arch/mips/tlb.cc | 6 ++++++ src/arch/mips/tlb.hh | 1 + 2 files changed, 7 insertions(+) (limited to 'src/arch/mips') diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc index 49ff2caba..8b106d437 100644 --- a/src/arch/mips/tlb.cc +++ b/src/arch/mips/tlb.cc @@ -346,6 +346,12 @@ TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) return NoFault; } +Fault +TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const +{ + return NoFault; +} + MipsISA::PTE & TLB::index(bool advance) diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh index e949d16d9..fdd590e85 100644 --- a/src/arch/mips/tlb.hh +++ b/src/arch/mips/tlb.hh @@ -118,6 +118,7 @@ class TLB : public BaseTLB * support the Checker model at the moment. */ Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode); + Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const; private: Fault translateInst(RequestPtr req, ThreadContext *tc); -- cgit v1.2.3