From 7b5a96f06b530db35637aca6f9d0f7a2ddfa6e60 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 8 Apr 2009 22:21:27 -0700
Subject: tlb: Don't separate the TLB classes into an instruction TLB and a
 data TLB

---
 src/arch/mips/MipsTLB.py | 20 +---------
 src/arch/mips/tlb.cc     | 97 ++++++++++--------------------------------------
 src/arch/mips/tlb.hh     | 32 +++-------------
 3 files changed, 27 insertions(+), 122 deletions(-)

(limited to 'src/arch/mips')

diff --git a/src/arch/mips/MipsTLB.py b/src/arch/mips/MipsTLB.py
index 41d46c572..16cbe6879 100644
--- a/src/arch/mips/MipsTLB.py
+++ b/src/arch/mips/MipsTLB.py
@@ -36,21 +36,5 @@ from BaseTLB import BaseTLB
 
 class MipsTLB(BaseTLB):
     type = 'MipsTLB'
-    abstract = True
-    size = Param.Int("TLB size")
-
-class MipsDTB(MipsTLB):
-    type = 'MipsDTB'
-    cxx_class = 'MipsISA::DTB'
-    size = 64
-
-class MipsITB(MipsTLB):
-    type = 'MipsITB'
-    cxx_class = 'MipsISA::ITB'
-    size = 64
-
-class MipsUTB(MipsTLB):
-    type = 'MipsUTB'
-    cxx_class = 'MipsISA::UTB'
-    size = 64
-
+    cxx_class = 'MipsISA::TLB'
+    size = Param.Int(64, "TLB size")
diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index eac44eba8..9343e35a3 100644
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -45,10 +45,7 @@
 #include "cpu/thread_context.hh"
 #include "sim/process.hh"
 #include "mem/page_table.hh"
-#include "params/MipsDTB.hh"
-#include "params/MipsITB.hh"
 #include "params/MipsTLB.hh"
-#include "params/MipsUTB.hh"
 
 
 using namespace std;
@@ -310,7 +307,7 @@ TLB::regStats()
 }
 
 Fault
-ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
+TLB::translateInst(RequestPtr req, ThreadContext *tc)
 {
 #if !FULL_SYSTEM
     Process * p = tc->getProcessPtr();
@@ -426,16 +423,8 @@ ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
 #endif
 }
 
-void
-ITB::translateTiming(RequestPtr req, ThreadContext *tc,
-        Translation *translation)
-{
-    assert(translation);
-    translation->finish(translateAtomic(req, tc), req, tc, false);
-}
-
 Fault
-DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write)
+TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
 {
 #if !FULL_SYSTEM
     Process * p = tc->getProcessPtr();
@@ -572,61 +561,25 @@ DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write)
 #endif
 }
 
+Fault
+TLB::translateAtomic(RequestPtr req, ThreadContext *tc,
+        bool write, bool execute)
+{
+    if (execute)
+        return translateInst(req, tc);
+    else
+        return translateData(req, tc, write);
+}
+
 void
-DTB::translateTiming(RequestPtr req, ThreadContext *tc,
-        Translation *translation, bool write)
+TLB::translateTiming(RequestPtr req, ThreadContext *tc,
+        Translation *translation, bool write, bool execute)
 {
     assert(translation);
-    translation->finish(translateAtomic(req, tc, write), req, tc, write);
+    translation->finish(translateAtomic(req, tc, write, execute),
+            req, tc, write, execute);
 }
 
-///////////////////////////////////////////////////////////////////////
-//
-//  Mips ITB
-//
-ITB::ITB(const Params *p)
-    : TLB(p)
-{}
-
-
-// void
-// ITB::regStats()
-// {
-//   /*    hits - causes failure for some reason
-//      .name(name() + ".hits")
-//      .desc("ITB hits");
-//     misses
-//      .name(name() + ".misses")
-//      .desc("ITB misses");
-//     acv
-//      .name(name() + ".acv")
-//      .desc("ITB acv");
-//     accesses
-//      .name(name() + ".accesses")
-//      .desc("ITB accesses");
-
-//      accesses = hits + misses + invalids; */
-// }
-
-
-
-///////////////////////////////////////////////////////////////////////
-//
-//  Mips DTB
-//
-DTB::DTB(const Params *p)
-    : TLB(p)
-{}
-
-///////////////////////////////////////////////////////////////////////
-//
-//  Mips UTB
-//
-UTB::UTB(const Params *p)
-    : ITB(p), DTB(p)
-{}
-
-
 
 MipsISA::PTE &
 TLB::index(bool advance)
@@ -639,20 +592,8 @@ TLB::index(bool advance)
     return *pte;
 }
 
-MipsISA::ITB *
-MipsITBParams::create()
-{
-    return new MipsISA::ITB(this);
-}
-
-MipsISA::DTB *
-MipsDTBParams::create()
-{
-    return new MipsISA::DTB(this);
-}
-
-MipsISA::UTB *
-MipsUTBParams::create()
+MipsISA::TLB *
+MipsTLBParams::create()
 {
-    return new MipsISA::UTB(this);
+    return new MipsISA::TLB(this);
 }
diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index dc0babf9a..fa2ed3f85 100644
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -43,8 +43,7 @@
 #include "arch/mips/pagetable.hh"
 #include "base/statistics.hh"
 #include "mem/request.hh"
-#include "params/MipsDTB.hh"
-#include "params/MipsITB.hh"
+#include "params/MipsTLB.hh"
 #include "sim/faults.hh"
 #include "sim/tlb.hh"
 #include "sim/sim_object.hh"
@@ -138,34 +137,15 @@ class TLB : public BaseTLB
     void unserialize(Checkpoint *cp, const std::string &section);
 
     void regStats();
-};
-
-class ITB : public TLB {
-  public:
-    typedef MipsTLBParams Params;
-    ITB(const Params *p);
-
-    Fault translateAtomic(RequestPtr req, ThreadContext *tc);
-    void translateTiming(RequestPtr req, ThreadContext *tc,
-            Translation *translation);
-};
-
-class DTB : public TLB {
-  public:
-    typedef MipsTLBParams Params;
-    DTB(const Params *p);
 
     Fault translateAtomic(RequestPtr req, ThreadContext *tc,
-            bool write = false);
+            bool write=false, bool execute=false);
     void translateTiming(RequestPtr req, ThreadContext *tc,
-            Translation *translation, bool write = false);
-};
-
-class UTB : public ITB, public DTB {
-  public:
-    typedef MipsTLBParams Params;
-    UTB(const Params *p);
+            Translation *translation, bool write=false, bool execute=false);
 
+  private:
+    Fault translateInst(RequestPtr req, ThreadContext *tc);
+    Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
 };
 
 }
-- 
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