From 9836d81c2bba97e36c43ca22feee1d51a12ce6ac Mon Sep 17 00:00:00 2001
From: Nathan Binkert <nate@binkert.org>
Date: Tue, 21 Oct 2008 07:12:53 -0700
Subject: style: Use the correct m5 style for things relating to interrupts.

---
 src/arch/mips/interrupts.cc |  6 +++---
 src/arch/mips/interrupts.hh | 28 +++++++++++++++-------------
 2 files changed, 18 insertions(+), 16 deletions(-)

(limited to 'src/arch/mips')

diff --git a/src/arch/mips/interrupts.cc b/src/arch/mips/interrupts.cc
index e04d22631..99f96fafc 100755
--- a/src/arch/mips/interrupts.cc
+++ b/src/arch/mips/interrupts.cc
@@ -76,7 +76,7 @@ static inline void setCauseIP_(ThreadContext *tc, uint8_t val) {
   intstatus &= ~(1 << int_num);
   }
 
-  void Interrupts::clear_all()
+  void Interrupts::clearAll()
   {
   DPRINTF(Interrupt, "Interrupts all cleared\n");
   intstatus = 0;
@@ -189,14 +189,14 @@ void Interrupts::clear(int int_num, int index)
     fatal("Must use Thread COntext when clearing MIPS Interrupts in M5");
 }
 
-void Interrupts::clear_all(ThreadContext *tc)
+void Interrupts::clearAll(ThreadContext *tc)
 {
     DPRINTF(Interrupt, "Interrupts all cleared\n");
     uint8_t intstatus = 0;
     setCauseIP_(tc, intstatus);
 }
 
-void Interrupts::clear_all()
+void Interrupts::clearAll()
 {
     fatal("Must use Thread COntext when clearing MIPS Interrupts in M5");
 }
diff --git a/src/arch/mips/interrupts.hh b/src/arch/mips/interrupts.hh
index 99a8f6fa0..af71e4636 100755
--- a/src/arch/mips/interrupts.hh
+++ b/src/arch/mips/interrupts.hh
@@ -57,23 +57,23 @@ class Interrupts
       //  for posting an interrupt. It sets a bit
       //  in intstatus corresponding to Cause IP*. The
       //  MIPS register Cause is updated by updateIntrInfo
-      //  which is called by check_interrupts
+      //  which is called by checkInterrupts
       //
       void post(int int_num, int index);
       // clear(int int_num, int index) is responsible
       //  for clearing an interrupt. It clear a bit
       //  in intstatus corresponding to Cause IP*. The
       //  MIPS register Cause is updated by updateIntrInfo
-      //  which is called by check_interrupts
+      //  which is called by checkInterrupts
       //
       void clear(int int_num, int index);
-      //  clear_all() is responsible
+      //  clearAll() is responsible
       //  for clearing all interrupts. It clears all bits
       //  in intstatus corresponding to Cause IP*. The
       //  MIPS register Cause is updated by updateIntrInfo
-      //  which is called by check_interrupts
+      //  which is called by checkInterrupts
       //
-      void clear_all();
+      void clearAll();
 
       // getInterrupt(ThreadContext * tc) checks if an interrupt
       //  should be returned. It ands the interrupt mask and
@@ -91,7 +91,7 @@ class Interrupts
       void updateIntrInfoCpuTimerIntr(ThreadContext *tc) const;
       bool onCpuTimerInterrupt(ThreadContext *tc) const;
 
-      bool check_interrupts(ThreadContext * tc) const{
+      bool checkInterrupts(ThreadContext *tc) const {
       //return (intstatus != 0) && !(tc->readPC() & 0x3);
       if (oncputimerintr == false){
       updateIntrInfo(tc);
@@ -119,7 +119,7 @@ class Interrupts
     //  for posting an interrupt. It sets a bit
     //  in intstatus corresponding to Cause IP*. The
     //  MIPS register Cause is updated by updateIntrInfo
-    //  which is called by check_interrupts
+    //  which is called by checkInterrupts
     //
     void post(int int_num, ThreadContext* tc);
     void post(int int_num, int index);
@@ -128,19 +128,19 @@ class Interrupts
     //  for clearing an interrupt. It clear a bit
     //  in intstatus corresponding to Cause IP*. The
     //  MIPS register Cause is updated by updateIntrInfo
-    //  which is called by check_interrupts
+    //  which is called by checkInterrupts
     //
     void clear(int int_num, ThreadContext* tc);
     void clear(int int_num, int index);
 
-    //  clear_all() is responsible
+    //  clearAll() is responsible
     //  for clearing all interrupts. It clears all bits
     //  in intstatus corresponding to Cause IP*. The
     //  MIPS register Cause is updated by updateIntrInfo
-    //  which is called by check_interrupts
+    //  which is called by checkInterrupts
     //
-    void clear_all(ThreadContext* tc);
-    void clear_all();
+    void clearAll(ThreadContext* tc);
+    void clearAll();
 
     // getInterrupt(ThreadContext * tc) checks if an interrupt
     //  should be returned. It ands the interrupt mask and
@@ -158,7 +158,9 @@ class Interrupts
     bool interruptsPending(ThreadContext *tc) const;
     bool onCpuTimerInterrupt(ThreadContext *tc) const;
 
-    bool check_interrupts(ThreadContext * tc) const{
+    bool
+    checkInterrupts(ThreadContext *tc) const
+    {
         return interruptsPending(tc);
     }
 
-- 
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