From 98cf57fb89b76a8ca423083d52cc647c7923fe51 Mon Sep 17 00:00:00 2001
From: Geoffrey Blake <geoffrey.blake@arm.com>
Date: Fri, 9 Mar 2012 09:59:28 -0500
Subject: CheckerCPU: Add function stubs to non-ARM ISA source to compile with
 CheckerCPU

Making the CheckerCPU a runtime time option requires the code to be compatible
with ISAs other than ARM.  This patch adds the appropriate function
stubs to allow compilation.
---
 src/arch/mips/tlb.cc | 7 +++++++
 src/arch/mips/tlb.hh | 5 +++++
 2 files changed, 12 insertions(+)

(limited to 'src/arch/mips')

diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index cd6d47d1e..49ff2caba 100644
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -339,6 +339,13 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
     translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
 }
 
+Fault
+TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
+{
+    panic("Not implemented\n");
+    return NoFault;
+}
+
 
 MipsISA::PTE &
 TLB::index(bool advance)
diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index 834431536..e949d16d9 100644
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -114,6 +114,11 @@ class TLB : public BaseTLB
     void translateTiming(RequestPtr req, ThreadContext *tc,
             Translation *translation, Mode mode);
 
+    /** Function stub for CheckerCPU compilation issues. MIPS does not
+     *  support the Checker model at the moment.
+     */
+    Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
+
   private:
     Fault translateInst(RequestPtr req, ThreadContext *tc);
     Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
-- 
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