From b7af65f414d34cb6b3817bc748fd053f505b0fea Mon Sep 17 00:00:00 2001 From: Stephen Hines Date: Tue, 20 May 2008 14:04:53 -0400 Subject: SCons: Fixing SCons bug 2006 issues for non-alpha ISAs --HG-- extra : convert_revision : 26e3edef06d6f82aaf162825c151d18faadd6e72 --- src/arch/mips/SConscript | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/arch/mips') diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript index 8be445c99..844e7ba15 100644 --- a/src/arch/mips/SConscript +++ b/src/arch/mips/SConscript @@ -33,6 +33,9 @@ Import('*') if env['TARGET_ISA'] == 'mips': +# Workaround for bug in SCons version > 0.97d20071212 +# Scons bug id: 2006 M5 Bug id: 308 + Dir('isa/formats') Source('faults.cc') Source('regfile/int_regfile.cc') Source('regfile/float_regfile.cc') -- cgit v1.2.3 From ce43e46576ccf09d56aeb7021d3decd75d08d90c Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Sat, 14 Jun 2008 12:57:21 -0700 Subject: Fix various SWIG warnings --- src/arch/mips/MipsTLB.py | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/MipsTLB.py b/src/arch/mips/MipsTLB.py index ce8847365..1d0244e22 100644 --- a/src/arch/mips/MipsTLB.py +++ b/src/arch/mips/MipsTLB.py @@ -33,10 +33,8 @@ from m5.SimObject import SimObject from m5.params import * class MipsTLB(SimObject): - abstract = True type = 'MipsTLB' - cxx_namespace = 'MipsISA' - cxx_class = 'TLB' + abstract = True size = Param.Int("TLB size") class MipsDTB(MipsTLB): -- cgit v1.2.3 From c5fbbf376a6be4bb3ad7ddc64841450541c16db6 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 1 Jul 2008 10:24:19 -0400 Subject: Change everything to use the cached virtPort rather than created their own each time. This appears to work, but I don't want to commit it until it gets tested a lot more. I haven't deleted the functionality in this patch that will come later, but one question is how to enforce encourage objects that call getVirtPort() to not cache the virtual port since if the CPU changes out from under them it will be worse than useless. Perhaps a null function like delVirtPort() is still useful in that case. --- src/arch/mips/utility.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc index c254811fa..52c52f8e7 100644 --- a/src/arch/mips/utility.cc +++ b/src/arch/mips/utility.cc @@ -59,7 +59,7 @@ getArgument(ThreadContext *tc, int number, bool fp) return tc->readIntReg(ArgumentReg[number]); } else { Addr sp = tc->readIntReg(StackPointerReg); - VirtualPort *vp = tc->getVirtPort(tc); + VirtualPort *vp = tc->getVirtPort(); uint64_t arg = vp->read(sp + (number-NumArgumentRegs) * sizeof(uint64_t)); tc->delVirtPort(vp); -- cgit v1.2.3 From a4a7a09e9622d6ad1ca91a4df253b9768c73de90 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 1 Jul 2008 10:25:07 -0400 Subject: Remove delVirtPort() and make getVirtPort() only return cached version. --- src/arch/mips/linux/system.cc | 1 - src/arch/mips/stacktrace.cc | 4 ---- src/arch/mips/utility.cc | 1 - 3 files changed, 6 deletions(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/linux/system.cc b/src/arch/mips/linux/system.cc index bed863e9d..23062c96b 100644 --- a/src/arch/mips/linux/system.cc +++ b/src/arch/mips/linux/system.cc @@ -168,7 +168,6 @@ LinuxMipsSystem::setDelayLoop(ThreadContext *tc) vp = tc->getVirtPort(); vp->writeHtoG(addr, (uint32_t)((cpuFreq / intrFreq) * 0.9988)); - tc->delVirtPort(vp); } } diff --git a/src/arch/mips/stacktrace.cc b/src/arch/mips/stacktrace.cc index 6c6f6bb3c..482d264e8 100644 --- a/src/arch/mips/stacktrace.cc +++ b/src/arch/mips/stacktrace.cc @@ -70,8 +70,6 @@ ProcessInfo::ProcessInfo(ThreadContext *_tc) // if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_comm", addr)) // panic("thread info not compiled into kernel\n"); // name_off = vp->readGtoH(addr); - - tc->delVirtPort(vp); } Addr @@ -87,7 +85,6 @@ ProcessInfo::task(Addr ksp) const vp = tc->getVirtPort(); tsk = vp->readGtoH(base + task_off); - tc->delVirtPort(vp); return tsk; } @@ -105,7 +102,6 @@ ProcessInfo::pid(Addr ksp) const vp = tc->getVirtPort(); pd = vp->readGtoH(task + pid_off); - tc->delVirtPort(vp); return pd; } diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc index 52c52f8e7..36cf76c67 100644 --- a/src/arch/mips/utility.cc +++ b/src/arch/mips/utility.cc @@ -62,7 +62,6 @@ getArgument(ThreadContext *tc, int number, bool fp) VirtualPort *vp = tc->getVirtPort(); uint64_t arg = vp->read(sp + (number-NumArgumentRegs) * sizeof(uint64_t)); - tc->delVirtPort(vp); return arg; } #else -- cgit v1.2.3 From 2cd04fd6da67d874fd4e563ed05707a42ff0598f Mon Sep 17 00:00:00 2001 From: Michael Adler Date: Wed, 23 Jul 2008 14:41:33 -0700 Subject: syscalls: Add a bunch of missing system calls. readlink, umask, truncate, ftruncate, mkdir, and getcwd. --- src/arch/mips/linux/process.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/linux/process.cc b/src/arch/mips/linux/process.cc index 06e6e2cf4..8a13d0f18 100644 --- a/src/arch/mips/linux/process.cc +++ b/src/arch/mips/linux/process.cc @@ -160,7 +160,7 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = { /* 36 */ SyscallDesc("sync", unimplementedFunc), /* 37 */ SyscallDesc("kill", unimplementedFunc), /* 38 */ SyscallDesc("rename", unimplementedFunc), - /* 39 */ SyscallDesc("mkdir", unimplementedFunc), + /* 39 */ SyscallDesc("mkdir", mkdirFunc), /* 40 */ SyscallDesc("rmdir", unimplementedFunc), /* 41 */ SyscallDesc("dup", unimplementedFunc), /* 42 */ SyscallDesc("pipe", pipePseudoFunc), @@ -181,7 +181,7 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = { /* 57 */ SyscallDesc("setpgid", unimplementedFunc), /* 58 */ SyscallDesc("ulimit", unimplementedFunc), /* 59 */ SyscallDesc("unused#59", unimplementedFunc), - /* 60 */ SyscallDesc("umask", unimplementedFunc), + /* 60 */ SyscallDesc("umask", umaskFunc), /* 61 */ SyscallDesc("chroot", unimplementedFunc), /* 62 */ SyscallDesc("ustat", unimplementedFunc), /* 63 */ SyscallDesc("dup2", unimplementedFunc), @@ -206,7 +206,7 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = { /* 82 */ SyscallDesc("reserved#82", unimplementedFunc), /* 83 */ SyscallDesc("symlink", unimplementedFunc), /* 84 */ SyscallDesc("unused#84", unimplementedFunc), - /* 85 */ SyscallDesc("readlink", unimplementedFunc), + /* 85 */ SyscallDesc("readlink", readlinkFunc), /* 86 */ SyscallDesc("uselib", unimplementedFunc), /* 87 */ SyscallDesc("swapon", gethostnameFunc), /* 88 */ SyscallDesc("reboot", unimplementedFunc), @@ -324,7 +324,7 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = { /* 200 */ SyscallDesc("pread64", unimplementedFunc), /* 201 */ SyscallDesc("pwrite64", unimplementedFunc), /* 202 */ SyscallDesc("chown", unimplementedFunc), - /* 203 */ SyscallDesc("getcwd", unimplementedFunc), + /* 203 */ SyscallDesc("getcwd", getcwdFunc), /* 204 */ SyscallDesc("capget", unimplementedFunc), /* 205 */ SyscallDesc("capset", unimplementedFunc), /* 206 */ SyscallDesc("sigalstack", unimplementedFunc), -- cgit v1.2.3 From ee62a0fec8e63f45f816c61ab9fb28aba7414185 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Mon, 11 Aug 2008 12:22:16 -0700 Subject: params: Convert the CPU objects to use the auto generated param structs. A whole bunch of stuff has been converted to use the new params stuff, but the CPU wasn't one of them. While we're at it, make some things a bit more stylish. Most of the work was done by Gabe, I just cleaned stuff up a bit more at the end. --- src/arch/mips/regfile/misc_regfile.cc | 103 +++++++++++++++++----------------- 1 file changed, 53 insertions(+), 50 deletions(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/regfile/misc_regfile.cc b/src/arch/mips/regfile/misc_regfile.cc index dc6ae0baf..407851007 100755 --- a/src/arch/mips/regfile/misc_regfile.cc +++ b/src/arch/mips/regfile/misc_regfile.cc @@ -40,6 +40,8 @@ #include "cpu/base.hh" #include "cpu/exetrace.hh" +#include "params/DerivO3CPU.hh" + using namespace std; std::string MiscRegFile::miscRegNames[NumMiscRegs] = @@ -170,11 +172,12 @@ void MiscRegFile::reset(std::string core_name, unsigned num_threads, unsigned num_vpes, BaseCPU *_cpu) { - DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n", num_threads, num_vpes); cpu = _cpu; - const BaseCPU::Params *p = _cpu->params; + + TheISA::CoreSpecific &cp = cpu->coreParams; + // Do Default CP0 initialization HERE // Do Initialization for MT cores here (eventually use @@ -183,10 +186,10 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads, DPRINTF(MipsPRA, "Initializing CP0 State.... "); MiscReg ProcID = readRegNoEffect(PRId); - replaceBits(ProcID,PRIdCoOp_HI,PRIdCoOp_LO,p->coreParams.CP0_PRId_CompanyOptions); - replaceBits(ProcID,PRIdCoID_HI,PRIdCoID_LO,p->coreParams.CP0_PRId_CompanyID); - replaceBits(ProcID,PRIdProc_ID_HI,PRIdProc_ID_LO,p->coreParams.CP0_PRId_ProcessorID); - replaceBits(ProcID,PRIdRev_HI,PRIdRev_LO,p->coreParams.CP0_PRId_Revision); + replaceBits(ProcID,PRIdCoOp_HI,PRIdCoOp_LO,cp.CP0_PRId_CompanyOptions); + replaceBits(ProcID,PRIdCoID_HI,PRIdCoID_LO,cp.CP0_PRId_CompanyID); + replaceBits(ProcID,PRIdProc_ID_HI,PRIdProc_ID_LO,cp.CP0_PRId_ProcessorID); + replaceBits(ProcID,PRIdRev_HI,PRIdRev_LO,cp.CP0_PRId_Revision); setRegNoEffect(PRId,ProcID); // Now, create Write Mask for ProcID register MiscReg ProcID_Mask = 0; // Read-Only register @@ -195,11 +198,11 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads, // Config MiscReg cfg = readRegNoEffect(Config); - replaceBits(cfg, Config_BE_HI, Config_BE_LO, p->coreParams.CP0_Config_BE); - replaceBits(cfg, Config_AT_HI, Config_AT_LO, p->coreParams.CP0_Config_AT); - replaceBits(cfg, Config_AR_HI, Config_AR_LO, p->coreParams.CP0_Config_AR); - replaceBits(cfg, Config_MT_HI, Config_MT_LO, p->coreParams.CP0_Config_MT); - replaceBits(cfg, Config_VI_HI, Config_VI_LO, p->coreParams.CP0_Config_VI); + replaceBits(cfg, Config_BE_HI, Config_BE_LO, cp.CP0_Config_BE); + replaceBits(cfg, Config_AT_HI, Config_AT_LO, cp.CP0_Config_AT); + replaceBits(cfg, Config_AR_HI, Config_AR_LO, cp.CP0_Config_AR); + replaceBits(cfg, Config_MT_HI, Config_MT_LO, cp.CP0_Config_MT); + replaceBits(cfg, Config_VI_HI, Config_VI_LO, cp.CP0_Config_VI); replaceBits(cfg, Config_M, 1); setRegNoEffect(Config, cfg); // Now, create Write Mask for Config register @@ -209,20 +212,20 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads, // Config1 MiscReg cfg1 = readRegNoEffect(Config1); - replaceBits(cfg1, Config1_MMUSize_HI, Config1_MMUSize_LO, p->coreParams.CP0_Config1_MMU); - replaceBits(cfg1, Config1_IS_HI, Config1_IS_LO, p->coreParams.CP0_Config1_IS); - replaceBits(cfg1, Config1_IL_HI, Config1_IL_LO, p->coreParams.CP0_Config1_IL); - replaceBits(cfg1, Config1_IA_HI, Config1_IA_LO, p->coreParams.CP0_Config1_IA); - replaceBits(cfg1, Config1_DS_HI, Config1_DS_LO, p->coreParams.CP0_Config1_DS); - replaceBits(cfg1, Config1_DL_HI, Config1_DL_LO, p->coreParams.CP0_Config1_DL); - replaceBits(cfg1, Config1_DA_HI, Config1_DA_LO, p->coreParams.CP0_Config1_DA); - replaceBits(cfg1, Config1_FP_HI, Config1_FP_LO, p->coreParams.CP0_Config1_FP); - replaceBits(cfg1, Config1_EP_HI, Config1_EP_LO, p->coreParams.CP0_Config1_EP); - replaceBits(cfg1, Config1_WR_HI, Config1_WR_LO, p->coreParams.CP0_Config1_WR); - replaceBits(cfg1, Config1_MD_HI, Config1_MD_LO, p->coreParams.CP0_Config1_MD); - replaceBits(cfg1, Config1_C2_HI, Config1_C2_LO, p->coreParams.CP0_Config1_C2); - replaceBits(cfg1, Config1_PC_HI, Config1_PC_LO, p->coreParams.CP0_Config1_PC); - replaceBits(cfg1, Config1_M, p->coreParams.CP0_Config1_M); + replaceBits(cfg1, Config1_MMUSize_HI, Config1_MMUSize_LO, cp.CP0_Config1_MMU); + replaceBits(cfg1, Config1_IS_HI, Config1_IS_LO, cp.CP0_Config1_IS); + replaceBits(cfg1, Config1_IL_HI, Config1_IL_LO, cp.CP0_Config1_IL); + replaceBits(cfg1, Config1_IA_HI, Config1_IA_LO, cp.CP0_Config1_IA); + replaceBits(cfg1, Config1_DS_HI, Config1_DS_LO, cp.CP0_Config1_DS); + replaceBits(cfg1, Config1_DL_HI, Config1_DL_LO, cp.CP0_Config1_DL); + replaceBits(cfg1, Config1_DA_HI, Config1_DA_LO, cp.CP0_Config1_DA); + replaceBits(cfg1, Config1_FP_HI, Config1_FP_LO, cp.CP0_Config1_FP); + replaceBits(cfg1, Config1_EP_HI, Config1_EP_LO, cp.CP0_Config1_EP); + replaceBits(cfg1, Config1_WR_HI, Config1_WR_LO, cp.CP0_Config1_WR); + replaceBits(cfg1, Config1_MD_HI, Config1_MD_LO, cp.CP0_Config1_MD); + replaceBits(cfg1, Config1_C2_HI, Config1_C2_LO, cp.CP0_Config1_C2); + replaceBits(cfg1, Config1_PC_HI, Config1_PC_LO, cp.CP0_Config1_PC); + replaceBits(cfg1, Config1_M, cp.CP0_Config1_M); setRegNoEffect(Config1, cfg1); // Now, create Write Mask for Config register MiscReg cfg1_Mask = 0; // Read Only Register @@ -231,15 +234,15 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads, // Config2 MiscReg cfg2 = readRegNoEffect(Config2); - replaceBits(cfg2, Config2_TU_HI, Config2_TU_LO, p->coreParams.CP0_Config2_TU); - replaceBits(cfg2, Config2_TS_HI, Config2_TS_LO, p->coreParams.CP0_Config2_TS); - replaceBits(cfg2, Config2_TL_HI, Config2_TL_LO, p->coreParams.CP0_Config2_TL); - replaceBits(cfg2, Config2_TA_HI, Config2_TA_LO, p->coreParams.CP0_Config2_TA); - replaceBits(cfg2, Config2_SU_HI, Config2_SU_LO, p->coreParams.CP0_Config2_SU); - replaceBits(cfg2, Config2_SS_HI, Config2_SS_LO, p->coreParams.CP0_Config2_SS); - replaceBits(cfg2, Config2_SL_HI, Config2_SL_LO, p->coreParams.CP0_Config2_SL); - replaceBits(cfg2, Config2_SA_HI, Config2_SA_LO, p->coreParams.CP0_Config2_SA); - replaceBits(cfg2, Config2_M, p->coreParams.CP0_Config2_M); + replaceBits(cfg2, Config2_TU_HI, Config2_TU_LO, cp.CP0_Config2_TU); + replaceBits(cfg2, Config2_TS_HI, Config2_TS_LO, cp.CP0_Config2_TS); + replaceBits(cfg2, Config2_TL_HI, Config2_TL_LO, cp.CP0_Config2_TL); + replaceBits(cfg2, Config2_TA_HI, Config2_TA_LO, cp.CP0_Config2_TA); + replaceBits(cfg2, Config2_SU_HI, Config2_SU_LO, cp.CP0_Config2_SU); + replaceBits(cfg2, Config2_SS_HI, Config2_SS_LO, cp.CP0_Config2_SS); + replaceBits(cfg2, Config2_SL_HI, Config2_SL_LO, cp.CP0_Config2_SL); + replaceBits(cfg2, Config2_SA_HI, Config2_SA_LO, cp.CP0_Config2_SA); + replaceBits(cfg2, Config2_M, cp.CP0_Config2_M); setRegNoEffect(Config2, cfg2); // Now, create Write Mask for Config register MiscReg cfg2_Mask = 0x7000F000; // Read Only Register @@ -248,14 +251,14 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads, // Config3 MiscReg cfg3 = readRegNoEffect(Config3); - replaceBits(cfg3, Config3_DSPP_HI, Config3_DSPP_LO, p->coreParams.CP0_Config3_DSPP); - replaceBits(cfg3, Config3_LPA_HI, Config3_LPA_LO, p->coreParams.CP0_Config3_LPA); - replaceBits(cfg3, Config3_VEIC_HI, Config3_VEIC_LO, p->coreParams.CP0_Config3_VEIC); - replaceBits(cfg3, Config3_VINT_HI, Config3_VINT_LO, p->coreParams.CP0_Config3_VInt); - replaceBits(cfg3, Config3_SP_HI, Config3_SP_LO, p->coreParams.CP0_Config3_SP); - replaceBits(cfg3, Config3_MT_HI, Config3_MT_LO, p->coreParams.CP0_Config3_MT); - replaceBits(cfg3, Config3_SM_HI, Config3_SM_LO, p->coreParams.CP0_Config3_SM); - replaceBits(cfg3, Config3_TL_HI, Config3_TL_LO, p->coreParams.CP0_Config3_TL); + replaceBits(cfg3, Config3_DSPP_HI, Config3_DSPP_LO, cp.CP0_Config3_DSPP); + replaceBits(cfg3, Config3_LPA_HI, Config3_LPA_LO, cp.CP0_Config3_LPA); + replaceBits(cfg3, Config3_VEIC_HI, Config3_VEIC_LO, cp.CP0_Config3_VEIC); + replaceBits(cfg3, Config3_VINT_HI, Config3_VINT_LO, cp.CP0_Config3_VInt); + replaceBits(cfg3, Config3_SP_HI, Config3_SP_LO, cp.CP0_Config3_SP); + replaceBits(cfg3, Config3_MT_HI, Config3_MT_LO, cp.CP0_Config3_MT); + replaceBits(cfg3, Config3_SM_HI, Config3_SM_LO, cp.CP0_Config3_SM); + replaceBits(cfg3, Config3_TL_HI, Config3_TL_LO, cp.CP0_Config3_TL); setRegNoEffect(Config3, cfg3); // Now, create Write Mask for Config register MiscReg cfg3_Mask = 0; // Read Only Register @@ -264,7 +267,7 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads, // EBase - CPUNum MiscReg EB = readRegNoEffect(EBase); - replaceBits(EB, EBase_CPUNum_HI, EBase_CPUNum_LO, p->coreParams.CP0_EBase_CPUNum); + replaceBits(EB, EBase_CPUNum_HI, EBase_CPUNum_LO, cp.CP0_EBase_CPUNum); replaceBits(EB, 31, 31, 1); setRegNoEffect(EBase, EB); // Now, create Write Mask for Config register @@ -275,7 +278,7 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads, // SRS Control - HSS (Highest Shadow Set) MiscReg SC = readRegNoEffect(SRSCtl); - replaceBits(SC, SRSCtl_HSS_HI,SRSCtl_HSS_LO,p->coreParams.CP0_SrsCtl_HSS); + replaceBits(SC, SRSCtl_HSS_HI,SRSCtl_HSS_LO,cp.CP0_SrsCtl_HSS); setRegNoEffect(SRSCtl, SC); // Now, create Write Mask for the SRS Ctl register MiscReg SC_Mask = 0x0000F3C0; @@ -284,8 +287,8 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads, // IntCtl - IPTI, IPPCI MiscReg IC = readRegNoEffect(IntCtl); - replaceBits(IC, IntCtl_IPTI_HI,IntCtl_IPTI_LO,p->coreParams.CP0_IntCtl_IPTI); - replaceBits(IC, IntCtl_IPPCI_HI,IntCtl_IPPCI_LO,p->coreParams.CP0_IntCtl_IPPCI); + replaceBits(IC, IntCtl_IPTI_HI,IntCtl_IPTI_LO,cp.CP0_IntCtl_IPTI); + replaceBits(IC, IntCtl_IPPCI_HI,IntCtl_IPPCI_LO,cp.CP0_IntCtl_IPPCI); setRegNoEffect(IntCtl, IC); // Now, create Write Mask for the IntCtl register MiscReg IC_Mask = 0x000003E0; @@ -294,7 +297,7 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads, // Watch Hi - M - FIXME (More than 1 Watch register) MiscReg WHi = readRegNoEffect(WatchHi0); - replaceBits(WHi, WatchHi_M, p->coreParams.CP0_WatchHi_M); + replaceBits(WHi, WatchHi_M, cp.CP0_WatchHi_M); setRegNoEffect(WatchHi0, WHi); // Now, create Write Mask for the IntCtl register MiscReg wh_Mask = 0x7FFF0FFF; @@ -303,8 +306,8 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads, // Perf Ctr - M - FIXME (More than 1 PerfCnt Pair) MiscReg PCtr = readRegNoEffect(PerfCnt0); - replaceBits(PCtr, PerfCntCtl_M, p->coreParams.CP0_PerfCtr_M); - replaceBits(PCtr, PerfCntCtl_W, p->coreParams.CP0_PerfCtr_W); + replaceBits(PCtr, PerfCntCtl_M, cp.CP0_PerfCtr_M); + replaceBits(PCtr, PerfCntCtl_W, cp.CP0_PerfCtr_W); setRegNoEffect(PerfCnt0, PCtr); // Now, create Write Mask for the IntCtl register MiscReg pc_Mask = 0x00007FF; @@ -322,7 +325,7 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads, // PageGrain MiscReg pagegrain = readRegNoEffect(PageGrain); - replaceBits(pagegrain,PageGrain_ESP,p->coreParams.CP0_Config3_SP); + replaceBits(pagegrain,PageGrain_ESP,cp.CP0_Config3_SP); setRegNoEffect(PageGrain, pagegrain); // Now, create Write Mask for the IntCtl register MiscReg pg_Mask = 0x10000000; -- cgit v1.2.3 From 1b1a7e33e730db51f67bc2f124347afaa7b0e0e9 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Mon, 11 Aug 2008 14:47:49 -0700 Subject: style --- src/arch/mips/regfile/misc_regfile.cc | 143 +++++++++++++++++++++------------- src/arch/mips/regfile/misc_regfile.hh | 6 +- 2 files changed, 95 insertions(+), 54 deletions(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/regfile/misc_regfile.cc b/src/arch/mips/regfile/misc_regfile.cc index 407851007..b82a94103 100755 --- a/src/arch/mips/regfile/misc_regfile.cc +++ b/src/arch/mips/regfile/misc_regfile.cc @@ -45,39 +45,49 @@ using namespace std; std::string MiscRegFile::miscRegNames[NumMiscRegs] = -{"Index", "MVPControl", "MVPConf0", "MVPConf1", "", "", "", "", - "Random", "VPEControl", "VPEConf0", "VPEConf1", "YQMask", "VPESchedule", "VPEScheFBack", "VPEOpt", - "EntryLo0", "TCStatus", "TCBind", "TCRestart", "TCHalt", "TCContext", "TCSchedule", "TCScheFBack", - "EntryLo1", "", "", "", "", "", "", "", - "Context", "ContextConfig", "", "", "", "", "", "", - "PageMask", "PageGrain", "", "", "", "", "", "", - "Wired", "SRSConf0", "SRCConf1", "SRSConf2", "SRSConf3", "SRSConf4", "", "", - "HWREna", "", "", "", "", "", "", "", - "BadVAddr", "", "", "", "", "", "", "", - "Count", "", "", "", "", "", "", "", - "EntryHi", "", "", "", "", "", "", "", - "Compare", "", "", "", "", "", "", "", - "Status", "IntCtl", "SRSCtl", "SRSMap", "", "", "", "", - "Cause", "", "", "", "", "", "", "", - "EPC", "", "", "", "", "", "", "", - "PRId", "EBase", "", "", "", "", "", "", - "Config", "Config1", "Config2", "Config3", "", "", "", "", - "LLAddr", "", "", "", "", "", "", "", - "WatchLo0", "WatchLo1", "WatchLo2", "WatchLo3", "WatchLo4", "WatchLo5", "WatchLo6", "WatchLo7", - "WatchHi0", "WatchHi1", "WatchHi2", "WatchHi3", "WatchHi4", "WatchHi5", "WatchHi6", "WatchHi7", - "XCContext64", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "Debug", "TraceControl1", "TraceControl2", "UserTraceData", "TraceBPC", "", "", "", - "DEPC", "", "", "", "", "", "", "", - "PerfCnt0", "PerfCnt1", "PerfCnt2", "PerfCnt3", "PerfCnt4", "PerfCnt5", "PerfCnt6", "PerfCnt7", - "ErrCtl", "", "", "", "", "", "", "", - "CacheErr0", "CacheErr1", "CacheErr2", "CacheErr3", "", "", "", "", - "TagLo0", "DataLo1", "TagLo2", "DataLo3", "TagLo4", "DataLo5", "TagLo6", "DataLo7", - "TagHi0", "DataHi1", "TagHi2", "DataHi3", "TagHi4", "DataHi5", "TagHi6", "DataHi7", - "ErrorEPC", "", "", "", "", "", "", "", - "DESAVE", "", "", "", "", "", "", "", - "LLFlag" +{ + "Index", "MVPControl", "MVPConf0", "MVPConf1", "", "", "", "", + "Random", "VPEControl", "VPEConf0", "VPEConf1", + "YQMask", "VPESchedule", "VPEScheFBack", "VPEOpt", + "EntryLo0", "TCStatus", "TCBind", "TCRestart", + "TCHalt", "TCContext", "TCSchedule", "TCScheFBack", + "EntryLo1", "", "", "", "", "", "", "", + "Context", "ContextConfig", "", "", "", "", "", "", + "PageMask", "PageGrain", "", "", "", "", "", "", + "Wired", "SRSConf0", "SRCConf1", "SRSConf2", + "SRSConf3", "SRSConf4", "", "", + "HWREna", "", "", "", "", "", "", "", + "BadVAddr", "", "", "", "", "", "", "", + "Count", "", "", "", "", "", "", "", + "EntryHi", "", "", "", "", "", "", "", + "Compare", "", "", "", "", "", "", "", + "Status", "IntCtl", "SRSCtl", "SRSMap", "", "", "", "", + "Cause", "", "", "", "", "", "", "", + "EPC", "", "", "", "", "", "", "", + "PRId", "EBase", "", "", "", "", "", "", + "Config", "Config1", "Config2", "Config3", "", "", "", "", + "LLAddr", "", "", "", "", "", "", "", + "WatchLo0", "WatchLo1", "WatchLo2", "WatchLo3", + "WatchLo4", "WatchLo5", "WatchLo6", "WatchLo7", + "WatchHi0", "WatchHi1", "WatchHi2", "WatchHi3", + "WatchHi4", "WatchHi5", "WatchHi6", "WatchHi7", + "XCContext64", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "Debug", "TraceControl1", "TraceControl2", "UserTraceData", + "TraceBPC", "", "", "", + "DEPC", "", "", "", "", "", "", "", + "PerfCnt0", "PerfCnt1", "PerfCnt2", "PerfCnt3", + "PerfCnt4", "PerfCnt5", "PerfCnt6", "PerfCnt7", + "ErrCtl", "", "", "", "", "", "", "", + "CacheErr0", "CacheErr1", "CacheErr2", "CacheErr3", "", "", "", "", + "TagLo0", "DataLo1", "TagLo2", "DataLo3", + "TagLo4", "DataLo5", "TagLo6", "DataLo7", + "TagHi0", "DataHi1", "TagHi2", "DataHi3", + "TagHi4", "DataHi5", "TagHi6", "DataHi7", + "ErrorEPC", "", "", "", "", "", "", "", + "DESAVE", "", "", "", "", "", "", "", + "LLFlag" }; MiscRegFile::MiscRegFile() @@ -212,7 +222,8 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads, // Config1 MiscReg cfg1 = readRegNoEffect(Config1); - replaceBits(cfg1, Config1_MMUSize_HI, Config1_MMUSize_LO, cp.CP0_Config1_MMU); + replaceBits(cfg1, Config1_MMUSize_HI, Config1_MMUSize_LO, + cp.CP0_Config1_MMU); replaceBits(cfg1, Config1_IS_HI, Config1_IS_LO, cp.CP0_Config1_IS); replaceBits(cfg1, Config1_IL_HI, Config1_IL_LO, cp.CP0_Config1_IL); replaceBits(cfg1, Config1_IA_HI, Config1_IA_LO, cp.CP0_Config1_IA); @@ -334,12 +345,18 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads, // Status MiscReg stat = readRegNoEffect(Status); - // Only CU0 and IE are modified on a reset - everything else needs to be controlled - // on a per CPU model basis - // replaceBits(stat, Status_CU0_HI,Status_CU0_LO, 1); // Enable CP0 on reset + // Only CU0 and IE are modified on a reset - everything else needs + // to be controlled on a per CPU model basis + + // Enable CP0 on reset + // replaceBits(stat, Status_CU0_HI,Status_CU0_LO, 1); + + // Enable ERL bit on a reset + replaceBits(stat, Status_ERL_HI, Status_ERL_LO, 1); + + // Enable BEV bit on a reset + replaceBits(stat, Status_BEV_HI, Status_BEV_LO, 1); - replaceBits(stat, Status_ERL_HI, Status_ERL_LO, 1); // Enable ERL bit on a reset - replaceBits(stat, Status_BEV_HI, Status_BEV_LO, 1); // Enable BEV bit on a reset setRegNoEffect(Status, stat); // Now, create Write Mask for the Status register MiscReg stat_Mask = 0xFF78FF17; @@ -440,7 +457,8 @@ MiscRegFile::readRegNoEffect(int reg_idx, unsigned tid) unsigned reg_sel = (bankType[misc_reg] == perThreadContext) ? tid : getVPENum(tid); DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) (%lx).\n", - misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg),miscRegFile[misc_reg][reg_sel]); + misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg), + miscRegFile[misc_reg][reg_sel]); return miscRegFile[misc_reg][reg_sel]; } @@ -454,8 +472,10 @@ MiscRegFile::readReg(int reg_idx, int misc_reg = reg_idx - Ctrl_Base_DepTag; unsigned reg_sel = (bankType[misc_reg] == perThreadContext) ? tid : getVPENum(tid); - DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n", - misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg),miscRegFile[misc_reg][reg_sel]); + DPRINTF(MipsPRA, + "Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n", + misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg), + miscRegFile[misc_reg][reg_sel]); switch (misc_reg) @@ -471,7 +491,9 @@ MiscRegFile::setRegNoEffect(int reg_idx, const MiscReg &val, unsigned tid) int misc_reg = reg_idx - Ctrl_Base_DepTag; unsigned reg_sel = (bankType[misc_reg] == perThreadContext) ? tid : getVPENum(tid); - DPRINTF(MipsPRA, "[tid:%i]: Setting (direct set) CP0 Register:%u Select:%u (%s) to %#x.\n", + DPRINTF(MipsPRA, + "[tid:%i]: Setting (direct set) CP0 Register:%u " + "Select:%u (%s) to %#x.\n", tid, misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg), val); miscRegFile[misc_reg][reg_sel] = val; @@ -483,7 +505,9 @@ MiscRegFile::setRegMask(int reg_idx, const MiscReg &val, unsigned tid) int misc_reg = reg_idx - Ctrl_Base_DepTag; unsigned reg_sel = (bankType[misc_reg] == perThreadContext) ? tid : getVPENum(tid); - DPRINTF(MipsPRA,"[tid:%i]: Setting CP0 Register: %u Select: %u (%s) to %#x\n",tid, misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg), val); + DPRINTF(MipsPRA, + "[tid:%i]: Setting CP0 Register: %u Select: %u (%s) to %#x\n", + tid, misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg), val); miscRegFile_WriteMask[misc_reg][reg_sel] = val; } @@ -500,7 +524,9 @@ MiscRegFile::setReg(int reg_idx, const MiscReg &val, int reg_sel = (bankType[misc_reg] == perThreadContext) ? tid : getVPENum(tid); - DPRINTF(MipsPRA, "[tid:%i]: Setting CP0 Register:%u Select:%u (%s) to %#x, with effect.\n", + DPRINTF(MipsPRA, + "[tid:%i]: Setting CP0 Register:%u " + "Select:%u (%s) to %#x, with effect.\n", tid, misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg), val); MiscReg cp0_val = filterCP0Write(misc_reg, reg_sel, val); @@ -509,16 +535,28 @@ MiscRegFile::setReg(int reg_idx, const MiscReg &val, scheduleCP0Update(1); } -/** This method doesn't need to adjust the Control Register Offset since - it has already been done in the calling method (setRegWithEffect) */ -MiscReg MiscRegFile::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val) +/** + * This method doesn't need to adjust the Control Register Offset + * since it has already been done in the calling method + * (setRegWithEffect) +*/ +MiscReg +MiscRegFile::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val) { MiscReg retVal = val; - retVal &= miscRegFile_WriteMask[misc_reg][reg_sel]; // Mask off read-only regions + + // Mask off read-only regions + retVal &= miscRegFile_WriteMask[misc_reg][reg_sel]; MiscReg curVal = miscRegFile[misc_reg][reg_sel]; - curVal &= (~miscRegFile_WriteMask[misc_reg][reg_sel]); // Mask off current alue with inverse mask (clear writeable bits) + // Mask off current alue with inverse mask (clear writeable bits) + curVal &= (~miscRegFile_WriteMask[misc_reg][reg_sel]); retVal |= curVal; // Combine the two - DPRINTF(MipsPRA,"filterCP0Write: Mask: %lx, Inverse Mask: %lx, write Val: %x, current val: %lx, written val: %x\n",miscRegFile_WriteMask[misc_reg][reg_sel],~miscRegFile_WriteMask[misc_reg][reg_sel],val,miscRegFile[misc_reg][reg_sel],retVal); + DPRINTF(MipsPRA, + "filterCP0Write: Mask: %lx, Inverse Mask: %lx, write Val: %x, " + "current val: %lx, written val: %x\n", + miscRegFile_WriteMask[misc_reg][reg_sel], + ~miscRegFile_WriteMask[misc_reg][reg_sel], + val, miscRegFile[misc_reg][reg_sel], retVal); return retVal; } void @@ -563,7 +601,8 @@ MiscRegFile::updateCPU() } MiscRegFile::CP0Event::CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type) - : Event(&mainEventQueue, CPU_Tick_Pri), cp0(_cp0), cpu(_cpu), cp0EventType(e_type) + : Event(&mainEventQueue, CPU_Tick_Pri), cp0(_cp0), cpu(_cpu), + cp0EventType(e_type) { } void diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh index 5f19579b3..4bec9a49e 100644 --- a/src/arch/mips/regfile/misc_regfile.hh +++ b/src/arch/mips/regfile/misc_regfile.hh @@ -75,7 +75,8 @@ namespace MipsISA void clear(unsigned tid_or_vpn = 0); - void reset(std::string core_name, unsigned num_threads, unsigned num_vpes, BaseCPU *_cpu); + void reset(std::string core_name, unsigned num_threads, + unsigned num_vpes, BaseCPU *_cpu); void expandForMultithreading(unsigned num_threads, unsigned num_vpes); @@ -98,7 +99,8 @@ namespace MipsISA MiscReg filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val); void setRegMask(int misc_reg, const MiscReg &val, unsigned tid = 0); - void setRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0); + void setRegNoEffect(int misc_reg, const MiscReg &val, + unsigned tid = 0); //template void setReg(int misc_reg, const MiscReg &val, -- cgit v1.2.3 From 09a8fb0b5263d4b41b8206ce075a3f6923907d65 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Tue, 9 Sep 2008 16:27:17 -0700 Subject: style: this file did not conform to style --- src/arch/mips/regfile/int_regfile.cc | 44 ++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 24 deletions(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/regfile/int_regfile.cc b/src/arch/mips/regfile/int_regfile.cc index c46ecf0b3..4ffbcdfb8 100644 --- a/src/arch/mips/regfile/int_regfile.cc +++ b/src/arch/mips/regfile/int_regfile.cc @@ -37,7 +37,6 @@ using namespace MipsISA; using namespace std; - void IntRegFile::clear() { @@ -48,25 +47,27 @@ IntRegFile::clear() void IntRegFile::setShadowSet(int css) { - DPRINTF(MipsPRA,"Setting Shadow Set to :%d (%s)\n",css,currShadowSet); + DPRINTF(MipsPRA, "Setting Shadow Set to :%d (%s)\n", css, currShadowSet); currShadowSet = css; } IntReg IntRegFile::readReg(int intReg) { - if(intReg < NumIntRegs) - { // Regular GPR Read - DPRINTF(MipsPRA,"Reading Reg: %d, CurrShadowSet: %d\n",intReg,currShadowSet); - if(intReg >= NumIntArchRegs*NumShadowRegSets){ - return regs[intReg+NumIntRegs*currShadowSet]; - } - else { - return regs[(intReg + NumIntArchRegs*currShadowSet) % NumIntArchRegs]; + if (intReg < NumIntRegs) { + // Regular GPR Read + DPRINTF(MipsPRA, "Reading Reg: %d, CurrShadowSet: %d\n", intReg, + currShadowSet); + + if (intReg >= NumIntArchRegs * NumShadowRegSets) { + return regs[intReg + NumIntRegs * currShadowSet]; + } else { + int index = intReg + NumIntArchRegs * currShadowSet; + index = index % NumIntArchRegs; + return regs[index]; } - } - else - { // Read from shadow GPR .. probably called by RDPGPR + } else { + // Read from shadow GPR .. probably called by RDPGPR return regs[intReg]; } } @@ -75,20 +76,16 @@ Fault IntRegFile::setReg(int intReg, const IntReg &val) { if (intReg != ZeroReg) { - - if(intReg < NumIntRegs) - { - if(intReg >= NumIntArchRegs*NumShadowRegSets){ + if (intReg < NumIntRegs) { + if (intReg >= NumIntArchRegs * NumShadowRegSets) regs[intReg] = val; - } - else{ - regs[intReg+NumIntRegs*currShadowSet] = val; - } - } - else{ + else + regs[intReg + NumIntRegs * currShadowSet] = val; + } else { regs[intReg] = val; } } + return NoFault; } @@ -103,4 +100,3 @@ IntRegFile::unserialize(Checkpoint *cp, const std::string §ion) { UNSERIALIZE_ARRAY(regs, NumIntRegs); } - -- cgit v1.2.3 From 3a3e356f4e61e86f6f1427dd85cf1e41fa9125c0 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 10 Sep 2008 14:26:15 -0400 Subject: style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs --- src/arch/mips/isa_traits.hh | 10 +++++----- src/arch/mips/linux/linux.cc | 40 ++++++++++++++++++++-------------------- src/arch/mips/linux/linux.hh | 40 ++++++++++++++++++++-------------------- src/arch/mips/regfile/regfile.hh | 12 ++++++------ src/arch/mips/system.cc | 6 +++--- src/arch/mips/tlb.cc | 32 ++++++++++++++++---------------- src/arch/mips/tlb.hh | 8 ++++---- 7 files changed, 74 insertions(+), 74 deletions(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh index fe28ad601..d4d1de479 100644 --- a/src/arch/mips/isa_traits.hh +++ b/src/arch/mips/isa_traits.hh @@ -147,11 +147,11 @@ namespace MipsISA // MIPS modes enum mode_type { - mode_kernel = 0, // kernel - mode_supervisor = 1, // supervisor - mode_user = 2, // user mode + mode_kernel = 0, // kernel + mode_supervisor = 1, // supervisor + mode_user = 2, // user mode mode_debug = 3, // debug mode - mode_number // number of modes + mode_number // number of modes }; inline mode_type getOperatingMode(MiscReg Stat) @@ -209,7 +209,7 @@ namespace MipsISA const int SyscallPseudoReturnReg = ReturnValueReg2; const int SyscallSuccessReg = ArgumentReg3; - const int LogVMPageSize = 13; // 8K bytes + const int LogVMPageSize = 13; // 8K bytes const int VMPageSize = (1 << LogVMPageSize); const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned diff --git a/src/arch/mips/linux/linux.cc b/src/arch/mips/linux/linux.cc index 4499107d7..8745731dc 100644 --- a/src/arch/mips/linux/linux.cc +++ b/src/arch/mips/linux/linux.cc @@ -35,34 +35,34 @@ // open(2) flags translation table OpenFlagTransTable MipsLinux::openFlagTable[] = { #ifdef _MSC_VER - { MipsLinux::TGT_O_RDONLY, _O_RDONLY }, - { MipsLinux::TGT_O_WRONLY, _O_WRONLY }, - { MipsLinux::TGT_O_RDWR, _O_RDWR }, - { MipsLinux::TGT_O_APPEND, _O_APPEND }, - { MipsLinux::TGT_O_CREAT, _O_CREAT }, - { MipsLinux::TGT_O_TRUNC, _O_TRUNC }, - { MipsLinux::TGT_O_EXCL, _O_EXCL }, + { MipsLinux::TGT_O_RDONLY, _O_RDONLY }, + { MipsLinux::TGT_O_WRONLY, _O_WRONLY }, + { MipsLinux::TGT_O_RDWR, _O_RDWR }, + { MipsLinux::TGT_O_APPEND, _O_APPEND }, + { MipsLinux::TGT_O_CREAT, _O_CREAT }, + { MipsLinux::TGT_O_TRUNC, _O_TRUNC }, + { MipsLinux::TGT_O_EXCL, _O_EXCL }, #ifdef _O_NONBLOCK - { MipsLinux::TGT_O_NONBLOCK, _O_NONBLOCK }, + { MipsLinux::TGT_O_NONBLOCK, _O_NONBLOCK }, #endif #ifdef _O_NOCTTY - { MipsLinux::TGT_O_NOCTTY, _O_NOCTTY }, + { MipsLinux::TGT_O_NOCTTY, _O_NOCTTY }, #endif #ifdef _O_SYNC - { MipsLinux::TGT_O_SYNC, _O_SYNC }, + { MipsLinux::TGT_O_SYNC, _O_SYNC }, #endif #else /* !_MSC_VER */ - { MipsLinux::TGT_O_RDONLY, O_RDONLY }, - { MipsLinux::TGT_O_WRONLY, O_WRONLY }, - { MipsLinux::TGT_O_RDWR, O_RDWR }, - { MipsLinux::TGT_O_APPEND, O_APPEND }, - { MipsLinux::TGT_O_CREAT, O_CREAT }, - { MipsLinux::TGT_O_TRUNC, O_TRUNC }, - { MipsLinux::TGT_O_EXCL, O_EXCL }, - { MipsLinux::TGT_O_NONBLOCK, O_NONBLOCK }, - { MipsLinux::TGT_O_NOCTTY, O_NOCTTY }, + { MipsLinux::TGT_O_RDONLY, O_RDONLY }, + { MipsLinux::TGT_O_WRONLY, O_WRONLY }, + { MipsLinux::TGT_O_RDWR, O_RDWR }, + { MipsLinux::TGT_O_APPEND, O_APPEND }, + { MipsLinux::TGT_O_CREAT, O_CREAT }, + { MipsLinux::TGT_O_TRUNC, O_TRUNC }, + { MipsLinux::TGT_O_EXCL, O_EXCL }, + { MipsLinux::TGT_O_NONBLOCK, O_NONBLOCK }, + { MipsLinux::TGT_O_NOCTTY, O_NOCTTY }, #ifdef O_SYNC - { MipsLinux::TGT_O_SYNC, O_SYNC }, + { MipsLinux::TGT_O_SYNC, O_SYNC }, #endif #endif /* _MSC_VER */ }; diff --git a/src/arch/mips/linux/linux.hh b/src/arch/mips/linux/linux.hh index fcfaa18ea..0d71a3c58 100644 --- a/src/arch/mips/linux/linux.hh +++ b/src/arch/mips/linux/linux.hh @@ -49,21 +49,21 @@ class MipsLinux : public Linux //@{ /// open(2) flag values. - static const int TGT_O_RDONLY = 0x00000000; //!< O_RDONLY - static const int TGT_O_WRONLY = 0x00000001; //!< O_WRONLY - static const int TGT_O_RDWR = 0x00000002; //!< O_RDWR - static const int TGT_O_NONBLOCK = 0x00000080; //!< O_NONBLOCK - static const int TGT_O_APPEND = 0x00000008; //!< O_APPEND - static const int TGT_O_CREAT = 0x00000100; //!< O_CREAT - static const int TGT_O_TRUNC = 0x00000200; //!< O_TRUNC - static const int TGT_O_EXCL = 0x00000400; //!< O_EXCL - static const int TGT_O_NOCTTY = 0x00000800; //!< O_NOCTTY - static const int TGT_O_SYNC = 0x00000010; //!< O_SYNC - static const int TGT_O_DRD = 0x00010000; //!< O_DRD - static const int TGT_O_DIRECTIO = 0x00020000; //!< O_DIRECTIO - static const int TGT_O_CACHE = 0x00002000; //!< O_CACHE - static const int TGT_O_DSYNC = 0x00008000; //!< O_DSYNC - static const int TGT_O_RSYNC = 0x00040000; //!< O_RSYNC + static const int TGT_O_RDONLY = 0x00000000; //!< O_RDONLY + static const int TGT_O_WRONLY = 0x00000001; //!< O_WRONLY + static const int TGT_O_RDWR = 0x00000002; //!< O_RDWR + static const int TGT_O_NONBLOCK = 0x00000080; //!< O_NONBLOCK + static const int TGT_O_APPEND = 0x00000008; //!< O_APPEND + static const int TGT_O_CREAT = 0x00000100; //!< O_CREAT + static const int TGT_O_TRUNC = 0x00000200; //!< O_TRUNC + static const int TGT_O_EXCL = 0x00000400; //!< O_EXCL + static const int TGT_O_NOCTTY = 0x00000800; //!< O_NOCTTY + static const int TGT_O_SYNC = 0x00000010; //!< O_SYNC + static const int TGT_O_DRD = 0x00010000; //!< O_DRD + static const int TGT_O_DIRECTIO = 0x00020000; //!< O_DIRECTIO + static const int TGT_O_CACHE = 0x00002000; //!< O_CACHE + static const int TGT_O_DSYNC = 0x00008000; //!< O_DSYNC + static const int TGT_O_RSYNC = 0x00040000; //!< O_RSYNC //@} /// For mmap(). @@ -72,12 +72,12 @@ class MipsLinux : public Linux //@{ /// For getsysinfo(). static const unsigned GSI_PLATFORM_NAME = 103; //!< platform name as string - static const unsigned GSI_CPU_INFO = 59; //!< CPU information - static const unsigned GSI_PROC_TYPE = 60; //!< get proc_type + static const unsigned GSI_CPU_INFO = 59; //!< CPU information + static const unsigned GSI_PROC_TYPE = 60; //!< get proc_type static const unsigned GSI_MAX_CPU = 30; //!< max # cpu's on this machine - static const unsigned GSI_CPUS_IN_BOX = 55; //!< number of CPUs in system - static const unsigned GSI_PHYSMEM = 19; //!< Physical memory in KB - static const unsigned GSI_CLK_TCK = 42; //!< clock freq in Hz + static const unsigned GSI_CPUS_IN_BOX = 55; //!< number of CPUs in system + static const unsigned GSI_PHYSMEM = 19; //!< Physical memory in KB + static const unsigned GSI_CLK_TCK = 42; //!< clock freq in Hz //@} //@{ diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh index 8304b7cda..407d9b50a 100644 --- a/src/arch/mips/regfile/regfile.hh +++ b/src/arch/mips/regfile/regfile.hh @@ -48,15 +48,15 @@ namespace MipsISA { class RegFile { protected: - Addr pc; // program counter - Addr npc; // next-cycle program counter - Addr nnpc; // next-next-cycle program counter + Addr pc; // program counter + Addr npc; // next-cycle program counter + Addr nnpc; // next-next-cycle program counter // used to implement branch delay slot // not real register - IntRegFile intRegFile; // (signed) integer register file - FloatRegFile floatRegFile; // floating point register file - MiscRegFile miscRegFile; // control register file + IntRegFile intRegFile; // (signed) integer register file + FloatRegFile floatRegFile; // floating point register file + MiscRegFile miscRegFile; // control register file public: void clear(); diff --git a/src/arch/mips/system.cc b/src/arch/mips/system.cc index 605acfe32..bf86bb030 100755 --- a/src/arch/mips/system.cc +++ b/src/arch/mips/system.cc @@ -134,9 +134,9 @@ MipsSystem::~MipsSystem() * in the procedure value register (pv aka t12 == r27). This sequence * looks like the following: * - * opcode Ra Rb offset - * ldah gp,X(pv) 09 29 27 X - * lda gp,Y(gp) 08 29 29 Y + * opcode Ra Rb offset + * ldah gp,X(pv) 09 29 27 X + * lda gp,Y(gp) 08 29 29 Y * * for some constant offsets X and Y. The catch is that the linker * (or maybe even the compiler, I'm not sure) may recognize that the diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc index d78aefab4..7c3b6aed5 100644 --- a/src/arch/mips/tlb.cc +++ b/src/arch/mips/tlb.cc @@ -59,7 +59,7 @@ using namespace MipsISA; // MIPS TLB // -#define MODE2MASK(X) (1 << (X)) +#define MODE2MASK(X) (1 << (X)) TLB::TLB(const Params *p) : BaseTLB(p), size(p->size), nlu(0) @@ -91,7 +91,7 @@ TLB::lookup(Addr vpn, uint8_t asn) const Addr Mask = pte->Mask; Addr InvMask = ~Mask; Addr VPN = pte->VPN; - // warn("Valid: %d - %d\n",pte->V0,pte->V1); + // warn("Valid: %d - %d\n",pte->V0,pte->V1); if(((vpn & InvMask) == (VPN & InvMask)) && (pte->G || (asn == pte->asid))) { // We have a VPN + ASID Match retval = pte; @@ -389,7 +389,7 @@ ITB::translate(RequestPtr &req, ThreadContext *tc) } else {// Ok, this is really a match, set paddr - // hits++; + // hits++; Addr PAddr; if(EvenOdd == 0){ PAddr = pte->PFN0; @@ -406,7 +406,7 @@ ITB::translate(RequestPtr &req, ThreadContext *tc) } else { // Didn't find any match, return a TLB Refill Exception - // misses++; + // misses++; ItbRefillFault *Flt=new ItbRefillFault(); /* EntryHi VPN, ASID fields must be set */ Flt->EntryHi_Asid = Asid; @@ -494,7 +494,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) if(Valid == false) {//Invalid entry - // invalids++; + // invalids++; DtbInvalidFault *Flt = new DtbInvalidFault(); /* EntryHi VPN, ASID fields must be set */ Flt->EntryHi_Asid = Asid; @@ -512,7 +512,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) } else {// Ok, this is really a match, set paddr - // hits++; + // hits++; if(!Dirty) { TLBModifiedFault *Flt = new TLBModifiedFault(); @@ -544,7 +544,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) } else { // Didn't find any match, return a TLB Refill Exception - // misses++; + // misses++; DtbRefillFault *Flt=new DtbRefillFault(); /* EntryHi VPN, ASID fields must be set */ Flt->EntryHi_Asid = Asid; @@ -577,19 +577,19 @@ ITB::ITB(const Params *p) // ITB::regStats() // { // /* hits - causes failure for some reason -// .name(name() + ".hits") -// .desc("ITB hits"); +// .name(name() + ".hits") +// .desc("ITB hits"); // misses -// .name(name() + ".misses") -// .desc("ITB misses"); +// .name(name() + ".misses") +// .desc("ITB misses"); // acv -// .name(name() + ".acv") -// .desc("ITB acv"); +// .name(name() + ".acv") +// .desc("ITB acv"); // accesses -// .name(name() + ".accesses") -// .desc("ITB accesses"); +// .name(name() + ".accesses") +// .desc("ITB accesses"); -// accesses = hits + misses + invalids; */ +// accesses = hits + misses + invalids; */ // } diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh index 4333777ff..feb2509c5 100644 --- a/src/arch/mips/tlb.hh +++ b/src/arch/mips/tlb.hh @@ -84,11 +84,11 @@ class TLB : public BaseTLB { protected: typedef std::multimap PageTable; - PageTable lookupTable; // Quick lookup into page table + PageTable lookupTable; // Quick lookup into page table - MipsISA::PTE *table; // the Page Table - int size; // TLB Size - int nlu; // not last used entry (for replacement) + MipsISA::PTE *table; // the Page Table + int size; // TLB Size + int nlu; // not last used entry (for replacement) void nextnlu() { if (++nlu >= size) nlu = 0; } MipsISA::PTE *lookup(Addr vpn, uint8_t asn) const; -- cgit v1.2.3 From 0309c877f32d415122cfb59960ec41dba54ba3e3 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Fri, 26 Sep 2008 08:18:53 -0700 Subject: style: These files didn't even come close to following the M5 style guide. --- src/arch/mips/dsp.cc | 989 +++++++++++++++++++++++++-------------------------- src/arch/mips/dsp.hh | 285 ++++++++------- 2 files changed, 635 insertions(+), 639 deletions(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/dsp.cc b/src/arch/mips/dsp.cc index 8e2db3f0b..183016ee7 100755 --- a/src/arch/mips/dsp.cc +++ b/src/arch/mips/dsp.cc @@ -40,92 +40,84 @@ using namespace MipsISA; using namespace std; int32_t -MipsISA::bitrev( int32_t value ) +MipsISA::bitrev(int32_t value) { int32_t result = 0; - int i, shift; + int shift; - for( i=0; i<16; i++ ) - { - shift = 2*i - 15; + for (int i = 0; i < 16; i++) { + shift = 2 * i - 15; - if( shift < 0 ) - result |= (value & 1L<> shift; + result |= (value & 1 << i) >> shift; } return result; } uint64_t -MipsISA::dspSaturate( uint64_t value, int32_t fmt, int32_t sign, uint32_t *overflow ) +MipsISA::dspSaturate(uint64_t value, int32_t fmt, int32_t sign, + uint32_t *overflow) { - int64_t svalue; + int64_t svalue = (int64_t)value; - svalue = (int64_t)value; - - switch( sign ) - { + switch(sign) { case SIGNED: - if( svalue > (int64_t)FIXED_SMAX[fmt] ) - { + if (svalue > (int64_t)FIXED_SMAX[fmt]) { *overflow = 1; svalue = (int64_t)FIXED_SMAX[fmt]; - } - else if( svalue < (int64_t)FIXED_SMIN[fmt] ) - { + } else if (svalue < (int64_t)FIXED_SMIN[fmt]) { *overflow = 1; svalue = (int64_t)FIXED_SMIN[fmt]; } break; case UNSIGNED: - if( svalue > (int64_t)FIXED_UMAX[fmt] ) - { + if (svalue > (int64_t)FIXED_UMAX[fmt]) { *overflow = 1; svalue = FIXED_UMAX[fmt]; - } - else if( svalue < (int64_t)FIXED_UMIN[fmt] ) - { + } else if (svalue < (int64_t)FIXED_UMIN[fmt]) { *overflow = 1; svalue = FIXED_UMIN[fmt]; } break; } - return( (uint64_t)svalue ); + return (uint64_t)svalue; } uint64_t -MipsISA::checkOverflow( uint64_t value, int32_t fmt, int32_t sign, uint32_t *overflow ) +MipsISA::checkOverflow(uint64_t value, int32_t fmt, int32_t sign, + uint32_t *overflow) { - int64_t svalue; - - svalue = (int64_t)value; + int64_t svalue = (int64_t)value; - switch( sign ) + switch(sign) { case SIGNED: - if( svalue > (int64_t)FIXED_SMAX[fmt] || svalue < (int64_t)FIXED_SMIN[fmt] ) + if (svalue > (int64_t)FIXED_SMAX[fmt] || + svalue < (int64_t)FIXED_SMIN[fmt]) *overflow = 1; break; case UNSIGNED: - if( svalue > (int64_t)FIXED_UMAX[fmt] || svalue < (int64_t)FIXED_UMIN[fmt] ) + if (svalue > (int64_t)FIXED_UMAX[fmt] || + svalue < (int64_t)FIXED_UMIN[fmt]) *overflow = 1; break; } - return( (uint64_t)svalue ); + return (uint64_t)svalue; } uint64_t -MipsISA::signExtend( uint64_t value, int32_t fmt ) +MipsISA::signExtend(uint64_t value, int32_t fmt) { int32_t signpos = SIMD_NBITS[fmt]; - uint64_t sign = uint64_t(1)<<(signpos-1); + uint64_t sign = uint64_t(1) << (signpos - 1); uint64_t ones = ~(0ULL); - if( value & sign ) + if (value & sign) value |= (ones << signpos); // extend with ones else value &= (ones >> (64 - signpos)); // extend with zeros @@ -134,231 +126,230 @@ MipsISA::signExtend( uint64_t value, int32_t fmt ) } uint64_t -MipsISA::addHalfLsb( uint64_t value, int32_t lsbpos ) +MipsISA::addHalfLsb(uint64_t value, int32_t lsbpos) { - return( value += ULL(1) << (lsbpos-1) ); + return value += ULL(1) << (lsbpos - 1); } int32_t -MipsISA::dspAbs( int32_t a, int32_t fmt, uint32_t *dspctl ) +MipsISA::dspAbs(int32_t a, int32_t fmt, uint32_t *dspctl) { - int i = 0; int nvals = SIMD_NVALS[fmt]; int32_t result; int64_t svalue; uint32_t ouflag = 0; uint64_t a_values[SIMD_MAX_VALS]; - simdUnpack( a, a_values, fmt, SIGNED ); + simdUnpack(a, a_values, fmt, SIGNED); - for( i=0; i> 1; + for (int i = 0; i < nvals; i++) { + if (round) + a_values[i] = addHalfLsb(a_values[i] + b_values[i], 1) >> 1; else - a_values[i] = ( a_values[i] + b_values[i] ) >> 1; + a_values[i] = (a_values[i] + b_values[i]) >> 1; } - simdPack( a_values, &result, fmt ); + simdPack(a_values, &result, fmt); - return( result ); + return result; } int32_t -MipsISA::dspSub( int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl ) +MipsISA::dspSub(int32_t a, int32_t b, int32_t fmt, int32_t saturate, + int32_t sign, uint32_t *dspctl) { - int i = 0; int nvals = SIMD_NVALS[fmt]; int32_t result; uint32_t ouflag = 0; uint64_t a_values[SIMD_MAX_VALS]; uint64_t b_values[SIMD_MAX_VALS]; - simdUnpack( a, a_values, fmt, sign ); - simdUnpack( b, b_values, fmt, sign ); + simdUnpack(a, a_values, fmt, sign); + simdUnpack(b, b_values, fmt, sign); - for( i=0; i> 1; + if (round) + a_values[i] = addHalfLsb(a_values[i] - b_values[i], 1) >> 1; else - a_values[i] = ( a_values[i] - b_values[i] ) >> 1; + a_values[i] = (a_values[i] - b_values[i]) >> 1; } - simdPack( a_values, &result, fmt ); + simdPack(a_values, &result, fmt); - return( result ); + return result; } int32_t -MipsISA::dspShll( int32_t a, uint32_t sa, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl ) +MipsISA::dspShll(int32_t a, uint32_t sa, int32_t fmt, int32_t saturate, + int32_t sign, uint32_t *dspctl) { - int i = 0; int nvals = SIMD_NVALS[fmt]; int32_t result; uint32_t ouflag = 0; uint64_t a_values[SIMD_MAX_VALS]; - sa = bits( sa, SIMD_LOG2N[fmt]-1, 0 ); - simdUnpack( a, a_values, fmt, sign ); + sa = bits(sa, SIMD_LOG2N[fmt] - 1, 0); + simdUnpack(a, a_values, fmt, sign); - for( i=0; i> sa; - simdPack( a_values, &result, fmt ); + simdPack(a_values, &result, fmt); - return( result ); + return result; } int32_t -MipsISA::dspShra( int32_t a, uint32_t sa, int32_t fmt, int32_t round, int32_t sign, uint32_t *dspctl ) +MipsISA::dspShra(int32_t a, uint32_t sa, int32_t fmt, int32_t round, + int32_t sign, uint32_t *dspctl) { - int i = 0; int nvals = SIMD_NVALS[fmt]; int32_t result; uint64_t a_values[SIMD_MAX_VALS]; - sa = bits( sa, SIMD_LOG2N[fmt]-1, 0 ); + sa = bits(sa, SIMD_LOG2N[fmt] - 1, 0); - simdUnpack( a, a_values, fmt, SIGNED ); + simdUnpack(a, a_values, fmt, SIGNED); - for( i=0; i> sa; + for (int i = 0; i < nvals; i++) { + if (round) + a_values[i] = addHalfLsb(a_values[i], sa) >> sa; else a_values[i] = a_values[i] >> sa; } - simdPack( a_values, &result, fmt ); + simdPack(a_values, &result, fmt); - return( result ); + return result; } int32_t -MipsISA::dspMulq( int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t round, uint32_t *dspctl ) +MipsISA::dspMulq(int32_t a, int32_t b, int32_t fmt, int32_t saturate, + int32_t round, uint32_t *dspctl) { - int i = 0; int nvals = SIMD_NVALS[fmt]; int sa = SIMD_NBITS[fmt]; int32_t result; @@ -367,102 +358,104 @@ MipsISA::dspMulq( int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t r uint64_t b_values[SIMD_MAX_VALS]; int64_t temp; - simdUnpack( a, a_values, fmt, SIGNED ); - simdUnpack( b, b_values, fmt, SIGNED ); + simdUnpack(a, a_values, fmt, SIGNED); + simdUnpack(b, b_values, fmt, SIGNED); - for( i=0; i> sa; + for (int i = 0; i < nvals; i++) { + if (round) + temp = + (int64_t)addHalfLsb(a_values[i] * b_values[i] << 1, sa) >> sa; else temp = (int64_t)(a_values[i] * b_values[i]) >> (sa - 1); - if( a_values[i] == FIXED_SMIN[fmt] && - b_values[i] == FIXED_SMIN[fmt] ) - { + if (a_values[i] == FIXED_SMIN[fmt] && b_values[i] == FIXED_SMIN[fmt]) { ouflag = 1; - if( saturate ) + if (saturate) temp = FIXED_SMAX[fmt]; } a_values[i] = temp; } - simdPack( a_values, &result, fmt ); + simdPack(a_values, &result, fmt); - if( ouflag ) - writeDSPControl( dspctl, (ouflag<<5)<-1; i-- ) - { + for (int i = nvals - 1; i > -1; i--) { temp[i] = a_values[i] * b_values[i] << 1; - if( a_values[i] == FIXED_SMIN[fmt] && - b_values[i] == FIXED_SMIN[fmt] ) - { - temp[i] = FIXED_SMAX[fmt-1]; + if (a_values[i] == FIXED_SMIN[fmt] && b_values[i] == FIXED_SMIN[fmt]) { + temp[i] = FIXED_SMAX[fmt - 1]; ouflag = 1; } } dspac += temp[1] - temp[0]; - if( ouflag ) - *dspctl = insertBits( *dspctl, 16+ac, 16+ac, 1 ); + if (ouflag) + *dspctl = insertBits(*dspctl, 16 + ac, 16 + ac, 1); return dspac; } void -MipsISA::dspCmp( int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op, uint32_t *dspctl ) +MipsISA::dspCmp(int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op, + uint32_t *dspctl) { - int i = 0; int nvals = SIMD_NVALS[fmt]; int ccond = 0; uint64_t a_values[SIMD_MAX_VALS]; uint64_t b_values[SIMD_MAX_VALS]; - simdUnpack( a, a_values, fmt, sign ); - simdUnpack( b, b_values, fmt, sign ); + simdUnpack(a, a_values, fmt, sign); + simdUnpack(b, b_values, fmt, sign); - for( i=0; i>1)] << sa; break; - case MODE_R: out_values[i] = in_values[i] << sa; break; - case MODE_LA: out_values[i] = in_values[(i<<1)+1] << sa; break; - case MODE_RA: out_values[i] = in_values[i<<1] << sa; break; + for (int i = 0; i> 1)] << sa; + break; + case MODE_R: + out_values[i] = in_values[i] << sa; + break; + case MODE_LA: + out_values[i] = in_values[(i << 1) + 1] << sa; + break; + case MODE_RA: + out_values[i] = in_values[i << 1] << sa; + break; } } - simdPack( out_values, &result, outfmt ); + simdPack(out_values, &result, outfmt); - return( result ); + return result; } int32_t -MipsISA::dspPrecrqu( int32_t a, int32_t b, uint32_t *dspctl ) +MipsISA::dspPrecrqu(int32_t a, int32_t b, uint32_t *dspctl) { - int i = 0; uint64_t a_values[SIMD_MAX_VALS]; uint64_t b_values[SIMD_MAX_VALS]; uint64_t r_values[SIMD_MAX_VALS]; uint32_t ouflag = 0; int32_t result = 0; - simdUnpack( a, a_values, SIMD_FMT_PH, SIGNED ); - simdUnpack( b, b_values, SIMD_FMT_PH, SIGNED ); + simdUnpack(a, a_values, SIMD_FMT_PH, SIGNED); + simdUnpack(b, b_values, SIMD_FMT_PH, SIGNED); - for( i=0; i<2; i++ ) - { - r_values[i] = dspSaturate( (int64_t)b_values[i] >> SIMD_NBITS[SIMD_FMT_QB] - 1, - SIMD_FMT_QB, UNSIGNED, &ouflag ); - r_values[i+2] = dspSaturate( (int64_t)a_values[i] >> SIMD_NBITS[SIMD_FMT_QB] - 1, - SIMD_FMT_QB, UNSIGNED, &ouflag ); + for (int i = 0; i<2; i++) { + r_values[i] = + dspSaturate((int64_t)b_values[i] >> SIMD_NBITS[SIMD_FMT_QB] - 1, + SIMD_FMT_QB, UNSIGNED, &ouflag); + r_values[i + 2] = + dspSaturate((int64_t)a_values[i] >> SIMD_NBITS[SIMD_FMT_QB] - 1, + SIMD_FMT_QB, UNSIGNED, &ouflag); } - simdPack( r_values, &result, SIMD_FMT_QB ); + simdPack(r_values, &result, SIMD_FMT_QB); - if( ouflag ) - *dspctl = insertBits( *dspctl, 22, 22, 1 ); + if (ouflag) + *dspctl = insertBits(*dspctl, 22, 22, 1); return result; } int32_t -MipsISA::dspPrecrq( int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl ) +MipsISA::dspPrecrq(int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl) { uint64_t a_values[SIMD_MAX_VALS]; uint64_t b_values[SIMD_MAX_VALS]; @@ -965,245 +947,226 @@ MipsISA::dspPrecrq( int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl ) uint32_t ouflag = 0; int32_t result; - simdUnpack( a, a_values, fmt, SIGNED ); - simdUnpack( b, b_values, fmt, SIGNED ); + simdUnpack(a, a_values, fmt, SIGNED); + simdUnpack(b, b_values, fmt, SIGNED); - r_values[1] = dspSaturate( (int64_t)addHalfLsb( a_values[0], 16 ) >> 16, - fmt+1, SIGNED, &ouflag ); - r_values[0] = dspSaturate( (int64_t)addHalfLsb( b_values[0], 16 ) >> 16, - fmt+1, SIGNED, &ouflag ); + r_values[1] = dspSaturate((int64_t)addHalfLsb(a_values[0], 16) >> 16, + fmt + 1, SIGNED, &ouflag); + r_values[0] = dspSaturate((int64_t)addHalfLsb(b_values[0], 16) >> 16, + fmt + 1, SIGNED, &ouflag); - simdPack( r_values, &result, fmt+1 ); + simdPack(r_values, &result, fmt + 1); - if( ouflag ) - *dspctl = insertBits( *dspctl, 22, 22, 1 ); + if (ouflag) + *dspctl = insertBits(*dspctl, 22, 22, 1); return result; } int32_t -MipsISA::dspPrecrSra( int32_t a, int32_t b, int32_t sa, int32_t fmt, int32_t round ) +MipsISA::dspPrecrSra(int32_t a, int32_t b, int32_t sa, int32_t fmt, + int32_t round) { - int i = 0; int nvals = SIMD_NVALS[fmt]; uint64_t a_values[SIMD_MAX_VALS]; uint64_t b_values[SIMD_MAX_VALS]; uint64_t c_values[SIMD_MAX_VALS]; int32_t result = 0; - simdUnpack( a, a_values, fmt, SIGNED ); - simdUnpack( b, b_values, fmt, SIGNED ); + simdUnpack(a, a_values, fmt, SIGNED); + simdUnpack(b, b_values, fmt, SIGNED); - for( i=0; i> sa; - c_values[i+1] = addHalfLsb( a_values[i], sa ) >> sa; - } - else - { + for (int i = 0; i < nvals; i++) { + if (round) { + c_values[i] = addHalfLsb(b_values[i], sa) >> sa; + c_values[i + 1] = addHalfLsb(a_values[i], sa) >> sa; + } else { c_values[i] = b_values[i] >> sa; - c_values[i+1] = a_values[i] >> sa; + c_values[i + 1] = a_values[i] >> sa; } } - simdPack( c_values, &result, fmt+1 ); + simdPack(c_values, &result, fmt + 1); return result; } int32_t -MipsISA::dspPick( int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl ) +MipsISA::dspPick(int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl) { - int i = 0; int nvals = SIMD_NVALS[fmt]; int32_t result; uint64_t a_values[SIMD_MAX_VALS]; uint64_t b_values[SIMD_MAX_VALS]; uint64_t c_values[SIMD_MAX_VALS]; - simdUnpack( a, a_values, fmt, UNSIGNED ); - simdUnpack( b, b_values, fmt, UNSIGNED ); + simdUnpack(a, a_values, fmt, UNSIGNED); + simdUnpack(b, b_values, fmt, UNSIGNED); - for( i=0; i 0 ) - { - if( round ) - { - temp = (int64_t)addHalfLsb( dspac, sa ); + if (sa > 0) { + if (round) { + temp = (int64_t)addHalfLsb(dspac, sa); - if( dspac > 0 && temp < 0 ) - { + if (dspac > 0 && temp < 0) { ouflag = 1; - if( saturate ) + if (saturate) temp = FIXED_SMAX[SIMD_FMT_L]; } temp = temp >> sa; - } - else + } else { temp = dspac >> sa; - } - else + } + } else { temp = dspac; + } - dspac = checkOverflow( dspac, fmt, SIGNED, &ouflag ); + dspac = checkOverflow(dspac, fmt, SIGNED, &ouflag); - if( ouflag ) - { - *dspctl = insertBits( *dspctl, 23, 23, ouflag ); + if (ouflag) { + *dspctl = insertBits(*dspctl, 23, 23, ouflag); - if( saturate ) - result = (int32_t)dspSaturate( temp, fmt, SIGNED, &ouflag ); + if (saturate) + result = (int32_t)dspSaturate(temp, fmt, SIGNED, &ouflag); else result = (int32_t)temp; - } - else + } else { result = (int32_t)temp; + } - return( result ); + return result; } int32_t -MipsISA::dspExtp( int64_t dspac, int32_t size, uint32_t *dspctl ) +MipsISA::dspExtp(int64_t dspac, int32_t size, uint32_t *dspctl) { int32_t pos = 0; int32_t result = 0; - pos = bits( *dspctl, 5, 0 ); - size = bits( size, 4, 0 ); + pos = bits(*dspctl, 5, 0); + size = bits(size, 4, 0); - if( pos - (size+1) >= -1 ) - { - result = bits( dspac, pos, pos-size ); - *dspctl = insertBits( *dspctl, 14, 14, 0 ); - } - else - { + if (pos - (size + 1) >= -1) { + result = bits(dspac, pos, pos - size); + *dspctl = insertBits(*dspctl, 14, 14, 0); + } else { result = 0; - *dspctl = insertBits( *dspctl, 14, 14, 1 ); + *dspctl = insertBits(*dspctl, 14, 14, 1); } - return( result ); + return result; } int32_t -MipsISA::dspExtpd( int64_t dspac, int32_t size, uint32_t *dspctl ) +MipsISA::dspExtpd(int64_t dspac, int32_t size, uint32_t *dspctl) { int32_t pos = 0; int32_t result = 0; - pos = bits( *dspctl, 5, 0 ); - size = bits( size, 4, 0 ); - - if( pos - (size+1) >= -1 ) - { - result = bits( dspac, pos, pos-size ); - *dspctl = insertBits( *dspctl, 14, 14, 0 ); - if( pos - (size+1) >= 0 ) - *dspctl = insertBits( *dspctl, 5, 0, pos - (size+1) ); - else if( (pos - (size+1)) == -1 ) - *dspctl = insertBits( *dspctl, 5, 0, 63 ); - } - else - { + pos = bits(*dspctl, 5, 0); + size = bits(size, 4, 0); + + if (pos - (size + 1) >= -1) { + result = bits(dspac, pos, pos - size); + *dspctl = insertBits(*dspctl, 14, 14, 0); + if (pos - (size + 1) >= 0) + *dspctl = insertBits(*dspctl, 5, 0, pos - (size + 1)); + else if ((pos - (size + 1)) == -1) + *dspctl = insertBits(*dspctl, 5, 0, 63); + } else { result = 0; - *dspctl = insertBits( *dspctl, 14, 14, 1 ); + *dspctl = insertBits(*dspctl, 14, 14, 1); } - return( result ); + return result; } void -MipsISA::simdPack( uint64_t *values_ptr, int32_t *reg, int32_t fmt ) +MipsISA::simdPack(uint64_t *values_ptr, int32_t *reg, int32_t fmt) { - int i = 0; int nvals = SIMD_NVALS[fmt]; int nbits = SIMD_NBITS[fmt]; *reg = 0; - for( i=0; i Date: Fri, 26 Sep 2008 08:18:56 -0700 Subject: Use logical operator instead of bitwise operator for correctness. --- src/arch/mips/mt.hh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/mt.hh b/src/arch/mips/mt.hh index 6765c27a9..20658df28 100755 --- a/src/arch/mips/mt.hh +++ b/src/arch/mips/mt.hh @@ -220,7 +220,7 @@ yieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask) warn("%i: Deactivating Hardware Thread Context #%i", curTick, tc->getThreadNum()); } } else if (src_reg > 0) { - if (src_reg & !yield_mask != 0) { + if (src_reg && !yield_mask != 0) { unsigned vpe_control = tc->readMiscReg(VPEControl); tc->setMiscReg(VPEControl, insertBits(vpe_control, VPEC_EXCPT_HI, VPEC_EXCPT_LO, 2)); fault = new ThreadFault(); -- cgit v1.2.3 From ca4baf387134f75b5e78a22c4c18d63fb5f48201 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Fri, 26 Sep 2008 09:37:21 -0700 Subject: style: missed space after switch --- src/arch/mips/dsp.cc | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/dsp.cc b/src/arch/mips/dsp.cc index 183016ee7..fc3ae65d6 100755 --- a/src/arch/mips/dsp.cc +++ b/src/arch/mips/dsp.cc @@ -63,7 +63,7 @@ MipsISA::dspSaturate(uint64_t value, int32_t fmt, int32_t sign, { int64_t svalue = (int64_t)value; - switch(sign) { + switch (sign) { case SIGNED: if (svalue > (int64_t)FIXED_SMAX[fmt]) { *overflow = 1; @@ -93,7 +93,7 @@ MipsISA::checkOverflow(uint64_t value, int32_t fmt, int32_t sign, { int64_t svalue = (int64_t)value; - switch(sign) + switch (sign) { case SIGNED: if (svalue > (int64_t)FIXED_SMAX[fmt] || @@ -431,7 +431,7 @@ MipsISA::dspMuleu(int32_t a, int32_t b, int32_t mode, uint32_t *dspctl) simdUnpack(a, a_values, SIMD_FMT_QB, UNSIGNED); simdUnpack(b, b_values, SIMD_FMT_PH, UNSIGNED); - switch(mode) { + switch (mode) { case MODE_L: for (int i = 0; i < nvals; i++) b_values[i] = dspSaturate(a_values[i + 2] * b_values[i], @@ -466,7 +466,7 @@ MipsISA::dspMuleq(int32_t a, int32_t b, int32_t mode, uint32_t *dspctl) simdUnpack(a, a_values, SIMD_FMT_PH, SIGNED); simdUnpack(b, b_values, SIMD_FMT_PH, SIGNED); - switch(mode) { + switch (mode) { case MODE_L: for (int i = 0; i < nvals; i++) c_values[i] = dspSaturate(a_values[i + 1] * b_values[i + 1] << 1, @@ -504,7 +504,7 @@ MipsISA::dspDpaq(int64_t dspac, int32_t a, int32_t b, int32_t ac, simdUnpack(b, b_values, infmt, SIGNED); for (int i = 0; i < nvals; i++) { - switch(mode) { + switch (mode) { case MODE_X: if (a_values[nvals - 1 - i] == FIXED_SMIN[infmt] && b_values[i] == FIXED_SMIN[infmt]) { @@ -571,7 +571,7 @@ MipsISA::dspDpsq(int64_t dspac, int32_t a, int32_t b, int32_t ac, simdUnpack(b, b_values, infmt, SIGNED); for (int i = 0; i < nvals; i++) { - switch(mode) { + switch (mode) { case MODE_X: if (a_values[nvals - 1 - i] == FIXED_SMIN[infmt] && b_values[i] == FIXED_SMIN[infmt]) { @@ -634,7 +634,7 @@ MipsISA::dspDpa(int64_t dspac, int32_t a, int32_t b, int32_t ac, simdUnpack(b, b_values, fmt, sign); for (int i = 0; i < 2; i++) { - switch(mode) { + switch (mode) { case MODE_L: dspac += a_values[nvals - 1 - i] * b_values[nvals - 1 - i]; break; @@ -662,7 +662,7 @@ MipsISA::dspDps(int64_t dspac, int32_t a, int32_t b, int32_t ac, simdUnpack(b, b_values, fmt, sign); for (int i = 0; i < 2; i++) { - switch(mode) { + switch (mode) { case MODE_L: dspac -= a_values[nvals - 1 - i] * b_values[nvals - 1 - i]; break; @@ -692,7 +692,7 @@ MipsISA::dspMaq(int64_t dspac, int32_t a, int32_t b, int32_t ac, simdUnpack(b, b_values, fmt, SIGNED); for (int i = 0; i < nvals; i++) { - switch(mode) { + switch (mode) { case MODE_L: temp = a_values[i + 1] * b_values[i + 1] << 1; if (a_values[i + 1] == FIXED_SMIN[fmt] && @@ -780,7 +780,7 @@ MipsISA::dspCmp(int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op, for (int i = 0; i < nvals; i++) { int cc = 0; - switch(op) { + switch (op) { case CMP_EQ: cc = (a_values[i] == b_values[i]); break; @@ -812,7 +812,7 @@ MipsISA::dspCmpg(int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op) for (int i = 0; i < nvals; i++) { int cc = 0; - switch(op) { + switch (op) { case CMP_EQ: cc = (a_values[i] == b_values[i]); break; @@ -846,7 +846,7 @@ MipsISA::dspCmpgd(int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op, for (int i = 0; i < nvals; i++) { int cc = 0; - switch(op) { + switch (op) { case CMP_EQ: cc = (a_values[i] == b_values[i]); break; @@ -888,7 +888,7 @@ MipsISA::dspPrece(int32_t a, int32_t infmt, int32_t insign, int32_t outfmt, simdUnpack(a, in_values, infmt, insign); for (int i = 0; i> 1)] << sa; break; @@ -1140,7 +1140,7 @@ MipsISA::simdUnpack(int32_t reg, uint64_t *values_ptr, int32_t fmt, int32_t sign int nvals = SIMD_NVALS[fmt]; int nbits = SIMD_NBITS[fmt]; - switch(sign) { + switch (sign) { case SIGNED: for (int i = 0; i < nvals; i++) { uint64_t tmp = (uint64_t)bits(reg, nbits * (i + 1) - 1, nbits * i); -- cgit v1.2.3 From 0b30c345f17f928c99660d633147f24f4f0035bd Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Sat, 27 Sep 2008 21:03:45 -0700 Subject: alpha: Get rid fo the namespace called EV5. We're never going to do an alpha platform other than the one we've got. --- src/arch/mips/mips_core_specific.cc | 4 ++-- src/arch/mips/system.cc | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/mips_core_specific.cc b/src/arch/mips/mips_core_specific.cc index a17ebcdf3..80d856b0c 100755 --- a/src/arch/mips/mips_core_specific.cc +++ b/src/arch/mips/mips_core_specific.cc @@ -113,13 +113,13 @@ MipsISA::processInterrupts(CPU *cpu) /*int MipsISA::MiscRegFile::getInstAsid() { - return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); + return AlphaISA::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); } int MipsISA::MiscRegFile::getDataAsid() { - return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); + return AlphaISA::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); }*/ diff --git a/src/arch/mips/system.cc b/src/arch/mips/system.cc index bf86bb030..73bc33161 100755 --- a/src/arch/mips/system.cc +++ b/src/arch/mips/system.cc @@ -185,7 +185,7 @@ MipsSystem::setMipsAccess(Addr access) { Addr addr = 0; if (consoleSymtab->findAddress("m5MipsAccess", addr)) { - // virtPort.write(addr, htog(EV5::Phys2K0Seg(access))); + // virtPort.write(addr, htog(AlphaISA::Phys2K0Seg(access))); } else panic("could not find m5MipsAccess\n"); } -- cgit v1.2.3 From 8ea5176b7f4eac09d152dd63d0ba07962be9c865 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Sat, 27 Sep 2008 21:03:46 -0700 Subject: arch: TheISA shouldn't really ever be used in the arch directory. We should always refer to the specific ISA in that arch directory. This is especially necessary if we're ever going to make it to the point where we actually have heterogeneous systems. --- src/arch/mips/idle_event.cc | 2 +- src/arch/mips/linux/threadinfo.hh | 4 ++-- src/arch/mips/regfile/misc_regfile.cc | 2 +- src/arch/mips/stacktrace.cc | 2 +- src/arch/mips/stacktrace.hh | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/idle_event.cc b/src/arch/mips/idle_event.cc index d1d4f7c63..0aea08834 100644 --- a/src/arch/mips/idle_event.cc +++ b/src/arch/mips/idle_event.cc @@ -34,7 +34,7 @@ #include "arch/mips/kernel_stats.hh" #include "cpu/thread_context.hh" -using namespace TheISA; +using namespace MipsISA; void IdleStartEvent::process(ThreadContext *tc) diff --git a/src/arch/mips/linux/threadinfo.hh b/src/arch/mips/linux/threadinfo.hh index 25ee74dd3..b0d0cd811 100644 --- a/src/arch/mips/linux/threadinfo.hh +++ b/src/arch/mips/linux/threadinfo.hh @@ -55,7 +55,7 @@ class ThreadInfo CopyOut(tc, &data, addr, sizeof(T)); - data = TheISA::gtoh(data); + data = MipsISA::gtoh(data); return true; } @@ -77,7 +77,7 @@ class ThreadInfo Addr sp; if (!addr) - addr = tc->readMiscRegNoEffect(0/*TheISA::IPR_PALtemp23*/); + addr = tc->readMiscRegNoEffect(0/*MipsISA::IPR_PALtemp23*/); FunctionalPort *p = tc->getPhysPort(); p->readBlob(addr, (uint8_t *)&sp, sizeof(Addr)); diff --git a/src/arch/mips/regfile/misc_regfile.cc b/src/arch/mips/regfile/misc_regfile.cc index b82a94103..e81f940f5 100755 --- a/src/arch/mips/regfile/misc_regfile.cc +++ b/src/arch/mips/regfile/misc_regfile.cc @@ -186,7 +186,7 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads, num_threads, num_vpes); cpu = _cpu; - TheISA::CoreSpecific &cp = cpu->coreParams; + MipsISA::CoreSpecific &cp = cpu->coreParams; // Do Default CP0 initialization HERE diff --git a/src/arch/mips/stacktrace.cc b/src/arch/mips/stacktrace.cc index 482d264e8..04a9a0f18 100644 --- a/src/arch/mips/stacktrace.cc +++ b/src/arch/mips/stacktrace.cc @@ -159,7 +159,7 @@ StackTrace::trace(ThreadContext *_tc, bool is_call) // } // SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab; -// Addr ksp = tc->readIntReg(TheISA::StackPointerReg); +// Addr ksp = tc->readIntReg(MipsISA::StackPointerReg); // Addr bottom = ksp & ~0x3fff; // Addr addr; diff --git a/src/arch/mips/stacktrace.hh b/src/arch/mips/stacktrace.hh index e2424523f..4c02cc86c 100644 --- a/src/arch/mips/stacktrace.hh +++ b/src/arch/mips/stacktrace.hh @@ -61,7 +61,7 @@ class ProcessInfo class StackTrace { protected: - typedef TheISA::MachInst MachInst; + typedef MipsISA::MachInst MachInst; private: ThreadContext *tc; std::vector stack; -- cgit v1.2.3 From 80d9be86e616e819cc3c9a0bbc8a42a5beb41247 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Sat, 27 Sep 2008 21:03:49 -0700 Subject: gcc: Add extra parens to quell warnings. Even though we're not incorrect about operator precedence, let's add some parens in some particularly confusing places to placate GCC 4.3 so that we don't have to turn the warning off. Agreed that this is a bit of a pain for those users who get the order of operations correct, but it is likely to prevent bugs in certain cases. --- src/arch/mips/dsp.cc | 4 ++-- src/arch/mips/isa/decoder.isa | 26 +++++++++++++------------- src/arch/mips/pagetable.hh | 4 ++-- src/arch/mips/utility.cc | 2 +- 4 files changed, 18 insertions(+), 18 deletions(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/dsp.cc b/src/arch/mips/dsp.cc index fc3ae65d6..6e4f7afea 100755 --- a/src/arch/mips/dsp.cc +++ b/src/arch/mips/dsp.cc @@ -923,10 +923,10 @@ MipsISA::dspPrecrqu(int32_t a, int32_t b, uint32_t *dspctl) for (int i = 0; i<2; i++) { r_values[i] = - dspSaturate((int64_t)b_values[i] >> SIMD_NBITS[SIMD_FMT_QB] - 1, + dspSaturate((int64_t)b_values[i] >> (SIMD_NBITS[SIMD_FMT_QB] - 1), SIMD_FMT_QB, UNSIGNED, &ouflag); r_values[i + 2] = - dspSaturate((int64_t)a_values[i] >> SIMD_NBITS[SIMD_FMT_QB] - 1, + dspSaturate((int64_t)a_values[i] >> (SIMD_NBITS[SIMD_FMT_QB] - 1), SIMD_FMT_QB, UNSIGNED, &ouflag); } diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa index b1cd03ca1..0a12c4f6e 100644 --- a/src/arch/mips/isa/decoder.isa +++ b/src/arch/mips/isa/decoder.isa @@ -416,16 +416,16 @@ decode OPCODE_HI default Unknown::unknown() { Ctrl_Base_DepTag); break; case 25: - data = 0 | fcsr_val & 0xFE000000 >> 24 - | fcsr_val & 0x00800000 >> 23; + data = (fcsr_val & 0xFE000000 >> 24) + | (fcsr_val & 0x00800000 >> 23); break; case 26: - data = 0 | fcsr_val & 0x0003F07C; + data = fcsr_val & 0x0003F07C; break; case 28: - data = 0 | fcsr_val & 0x00000F80 - | fcsr_val & 0x01000000 >> 21 - | fcsr_val & 0x00000003; + data = (fcsr_val & 0x00000F80) + | (fcsr_val & 0x01000000 >> 21) + | (fcsr_val & 0x00000003); break; case 31: data = fcsr_val; @@ -1963,7 +1963,7 @@ decode OPCODE_HI default Unknown::unknown() { 0x0: decode OP_LO { format IntOp { 0x0: append({{ Rt.uw = (Rt.uw << RD) | bits(Rs.uw,RD-1,0); }}); - 0x1: prepend({{ Rt.uw = (Rt.uw >> RD) | (bits(Rs.uw,RD-1,0) << 32-RD); }}); + 0x1: prepend({{ Rt.uw = (Rt.uw >> RD) | (bits(Rs.uw, RD - 1, 0) << (32 - RD)); }}); } } 0x2: decode OP_LO { @@ -2050,11 +2050,11 @@ decode OPCODE_HI default Unknown::unknown() { format LoadUnalignedMemory { 0x2: lwl({{ uint32_t mem_shift = 24 - (8 * byte_offset); Rt.uw = mem_word << mem_shift | - Rt.uw & mask(mem_shift); + (Rt.uw & mask(mem_shift)); }}); 0x6: lwr({{ uint32_t mem_shift = 8 * byte_offset; - Rt.uw = Rt.uw & (mask(mem_shift) << (32 - mem_shift)) | - mem_word >> mem_shift; + Rt.uw = (Rt.uw & (mask(mem_shift) << (32 - mem_shift))) | + (mem_word >> mem_shift); }}); } } @@ -2069,12 +2069,12 @@ decode OPCODE_HI default Unknown::unknown() { format StoreUnalignedMemory { 0x2: swl({{ uint32_t reg_shift = 24 - (8 * byte_offset); uint32_t mem_shift = 32 - reg_shift; - mem_word = mem_word & (mask(reg_shift) << mem_shift) | - Rt.uw >> reg_shift; + mem_word = (mem_word & (mask(reg_shift) << mem_shift)) | + (Rt.uw >> reg_shift); }}); 0x6: swr({{ uint32_t reg_shift = 8 * byte_offset; mem_word = Rt.uw << reg_shift | - mem_word & (mask(reg_shift)); + (mem_word & (mask(reg_shift))); }}); } format CP0Control { diff --git a/src/arch/mips/pagetable.hh b/src/arch/mips/pagetable.hh index 8c43a7b0c..bbed94194 100755 --- a/src/arch/mips/pagetable.hh +++ b/src/arch/mips/pagetable.hh @@ -59,9 +59,9 @@ namespace MipsISA { Addr level3() const { return MipsISA::PteAddr(addr >> PageShift); } Addr level2() const - { return MipsISA::PteAddr(addr >> NPtePageShift + PageShift); } + { return MipsISA::PteAddr(addr >> (NPtePageShift + PageShift)); } Addr level1() const - { return MipsISA::PteAddr(addr >> 2 * NPtePageShift + PageShift); } + { return MipsISA::PteAddr(addr >> (2 * NPtePageShift + PageShift)); } }; // ITB/DTB page table entry diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc index 36cf76c67..1985c0f43 100644 --- a/src/arch/mips/utility.cc +++ b/src/arch/mips/utility.cc @@ -145,7 +145,7 @@ genCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val) { int cc_idx = (cc_num == 0) ? 23 : cc_num + 24; - fcsr = bits(fcsr, 31, cc_idx + 1) << cc_idx + 1 | + fcsr = bits(fcsr, 31, cc_idx + 1) << (cc_idx + 1) | cc_val << cc_idx | bits(fcsr, cc_idx - 1, 0); -- cgit v1.2.3 From 6c046a28dc6624f57655e5106568721972cbae1e Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Mon, 6 Oct 2008 02:07:04 -0400 Subject: fix shadow set bugs in MIPS code that caused out of bounds access... panic rdpgpr/wrpgpr instructions until a better impl. of MIPS shadow sets is available. --- src/arch/mips/isa/decoder.isa | 6 ++++-- src/arch/mips/isa_traits.hh | 2 ++ src/arch/mips/regfile/int_regfile.cc | 35 ++++++++++++++++++----------------- src/arch/mips/regfile/int_regfile.hh | 3 ++- src/arch/mips/regfile/misc_regfile.cc | 2 +- 5 files changed, 27 insertions(+), 21 deletions(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa index 0a12c4f6e..8af504e55 100644 --- a/src/arch/mips/isa/decoder.isa +++ b/src/arch/mips/isa/decoder.isa @@ -603,7 +603,8 @@ decode OPCODE_HI default Unknown::unknown() { 0xA: rdpgpr({{ if(Config_AR >= 1) { // Rev 2 of the architecture - Rd = xc->tcBase()->readIntReg(RT + NumIntRegs * SRSCtl_PSS); + panic("Shadow Sets Not Fully Implemented.\n"); + //Rd = xc->tcBase()->readIntReg(RT + NumIntRegs * SRSCtl_PSS); } else { @@ -613,7 +614,8 @@ decode OPCODE_HI default Unknown::unknown() { 0xE: wrpgpr({{ if(Config_AR >= 1) { // Rev 2 of the architecture - xc->tcBase()->setIntReg(RD + NumIntRegs * SRSCtl_PSS,Rt); + panic("Shadow Sets Not Fully Implemented.\n"); + //xc->tcBase()->setIntReg(RD + NumIntRegs * SRSCtl_PSS,Rt); // warn("Writing %d to %d, PSS: %d, SRS: %x\n",Rt,RD + NumIntRegs * SRSCtl_PSS, SRSCtl_PSS,SRSCtl); } else diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh index d4d1de479..3450c273e 100644 --- a/src/arch/mips/isa_traits.hh +++ b/src/arch/mips/isa_traits.hh @@ -181,6 +181,8 @@ namespace MipsISA const int NumIntRegs = NumIntArchRegs*NumShadowRegSets + NumIntSpecialRegs; //HI & LO Regs const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;// + const int TotalArchRegs = NumIntArchRegs * NumShadowRegSets; + // Static instruction parameters const int MaxInstSrcRegs = 10; const int MaxInstDestRegs = 8; diff --git a/src/arch/mips/regfile/int_regfile.cc b/src/arch/mips/regfile/int_regfile.cc index 4ffbcdfb8..88de4be94 100644 --- a/src/arch/mips/regfile/int_regfile.cc +++ b/src/arch/mips/regfile/int_regfile.cc @@ -44,6 +44,12 @@ IntRegFile::clear() currShadowSet=0; } +int +IntRegFile::readShadowSet() +{ + return currShadowSet; +} + void IntRegFile::setShadowSet(int css) { @@ -54,21 +60,17 @@ IntRegFile::setShadowSet(int css) IntReg IntRegFile::readReg(int intReg) { - if (intReg < NumIntRegs) { + if (intReg < NumIntArchRegs) { // Regular GPR Read DPRINTF(MipsPRA, "Reading Reg: %d, CurrShadowSet: %d\n", intReg, - currShadowSet); + currShadowSet); - if (intReg >= NumIntArchRegs * NumShadowRegSets) { - return regs[intReg + NumIntRegs * currShadowSet]; - } else { - int index = intReg + NumIntArchRegs * currShadowSet; - index = index % NumIntArchRegs; - return regs[index]; - } + return regs[intReg + NumIntArchRegs * currShadowSet]; } else { - // Read from shadow GPR .. probably called by RDPGPR - return regs[intReg]; + unsigned special_reg_num = intReg - NumIntArchRegs; + + // Read A Special Reg + return regs[TotalArchRegs + special_reg_num]; } } @@ -76,13 +78,12 @@ Fault IntRegFile::setReg(int intReg, const IntReg &val) { if (intReg != ZeroReg) { - if (intReg < NumIntRegs) { - if (intReg >= NumIntArchRegs * NumShadowRegSets) - regs[intReg] = val; - else - regs[intReg + NumIntRegs * currShadowSet] = val; + if (intReg < NumIntArchRegs) { + regs[intReg + NumIntArchRegs * currShadowSet] = val; } else { - regs[intReg] = val; + unsigned special_reg_num = intReg - NumIntArchRegs; + + regs[TotalArchRegs + special_reg_num] = val; } } diff --git a/src/arch/mips/regfile/int_regfile.hh b/src/arch/mips/regfile/int_regfile.hh index 8ddd276e6..0f453a382 100644 --- a/src/arch/mips/regfile/int_regfile.hh +++ b/src/arch/mips/regfile/int_regfile.hh @@ -48,7 +48,7 @@ namespace MipsISA } enum MiscIntRegNums { - LO = NumIntArchRegs*NumShadowRegSets, + LO = NumIntArchRegs, HI, DSPACX0, DSPLo1, @@ -72,6 +72,7 @@ namespace MipsISA int currShadowSet; public: void clear(); + int readShadowSet(); void setShadowSet(int css); IntReg readReg(int intReg); Fault setReg(int intReg, const IntReg &val); diff --git a/src/arch/mips/regfile/misc_regfile.cc b/src/arch/mips/regfile/misc_regfile.cc index e81f940f5..06523a8c9 100755 --- a/src/arch/mips/regfile/misc_regfile.cc +++ b/src/arch/mips/regfile/misc_regfile.cc @@ -40,7 +40,7 @@ #include "cpu/base.hh" #include "cpu/exetrace.hh" -#include "params/DerivO3CPU.hh" +//#include "params/DerivO3CPU.hh" using namespace std; -- cgit v1.2.3 From f57c286d2c3fceae84fde60f148f70305c846772 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Thu, 9 Oct 2008 00:09:26 -0700 Subject: O3: Generaize the O3 dynamic instruction class so it isn't split out by ISA. --HG-- rename : src/cpu/o3/dyn_inst.hh => src/cpu/o3/dyn_inst_decl.hh rename : src/cpu/o3/alpha/dyn_inst_impl.hh => src/cpu/o3/dyn_inst_impl.hh --- src/arch/mips/locked_mem.hh | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh index 34da79ed9..07dc9d588 100644 --- a/src/arch/mips/locked_mem.hh +++ b/src/arch/mips/locked_mem.hh @@ -49,11 +49,10 @@ template inline void handleLockedRead(XC *xc, Request *req) { - unsigned tid = req->getThreadNum(); - xc->setMiscRegNoEffect(LLAddr, req->getPaddr() & ~0xf, tid); - xc->setMiscRegNoEffect(LLFlag, true, tid); + xc->setMiscRegNoEffect(LLAddr, req->getPaddr() & ~0xf); + xc->setMiscRegNoEffect(LLFlag, true); DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link Address set to %x.\n", - tid, req->getPaddr() & ~0xf); + req->getThreadNum(), req->getPaddr() & ~0xf); } @@ -61,22 +60,20 @@ template inline bool handleLockedWrite(XC *xc, Request *req) { - unsigned tid = req->getThreadNum(); - if (req->isUncacheable()) { // Funky Turbolaser mailbox access...don't update // result register (see stq_c in decoder.isa) req->setExtraData(2); } else { // standard store conditional - bool lock_flag = xc->readMiscRegNoEffect(LLFlag, tid); - Addr lock_addr = xc->readMiscRegNoEffect(LLAddr, tid); + bool lock_flag = xc->readMiscRegNoEffect(LLFlag); + Addr lock_addr = xc->readMiscRegNoEffect(LLAddr); if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) { // Lock flag not set or addr mismatch in CPU; // don't even bother sending to memory system req->setExtraData(0); - xc->setMiscRegNoEffect(LLFlag, false, tid); + xc->setMiscRegNoEffect(LLFlag, false); // the rest of this code is not architectural; // it's just a debugging aid to help detect @@ -97,10 +94,10 @@ handleLockedWrite(XC *xc, Request *req) if (!lock_flag){ DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, Store Conditional Failed.\n", - tid); + req->getThreadNum()); } else if ((req->getPaddr() & ~0xf) != lock_addr) { DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, Store Conditional Failed.\n", - tid); + req->getThreadNum()); } // store conditional failed already, so don't issue it to mem return false; -- cgit v1.2.3 From e06321091d4e931ff1a4d753e56d76f9746c3cd2 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Thu, 9 Oct 2008 04:58:24 -0700 Subject: eventq: convert all usage of events to use the new API. For now, there is still a single global event queue, but this is necessary for making the steps towards a parallelized m5. --- src/arch/mips/regfile/misc_regfile.cc | 10 +++------- src/arch/mips/regfile/regfile.cc | 5 +++-- src/arch/mips/regfile/regfile.hh | 8 +++++--- 3 files changed, 11 insertions(+), 12 deletions(-) mode change 100755 => 100644 src/arch/mips/regfile/misc_regfile.cc (limited to 'src/arch/mips') diff --git a/src/arch/mips/regfile/misc_regfile.cc b/src/arch/mips/regfile/misc_regfile.cc old mode 100755 new mode 100644 index 06523a8c9..08487db90 --- a/src/arch/mips/regfile/misc_regfile.cc +++ b/src/arch/mips/regfile/misc_regfile.cc @@ -567,7 +567,7 @@ MiscRegFile::scheduleCP0Update(int delay) //schedule UPDATE CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0); - cp0_event->schedule(curTick + cpu->ticks(delay)); + cpu->schedule(cp0_event, curTick + cpu->ticks(delay)); } } @@ -601,8 +601,7 @@ MiscRegFile::updateCPU() } MiscRegFile::CP0Event::CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type) - : Event(&mainEventQueue, CPU_Tick_Pri), cp0(_cp0), cpu(_cpu), - cp0EventType(e_type) + : Event(CPU_Tick_Pri), cp0(_cp0), cpu(_cpu), cp0EventType(e_type) { } void @@ -627,10 +626,7 @@ MiscRegFile::CP0Event::description() const void MiscRegFile::CP0Event::scheduleEvent(int delay) { - if (squashed()) - reschedule(curTick + cpu->ticks(delay)); - else if (!scheduled()) - schedule(curTick + cpu->ticks(delay)); + cpu->reschedule(this, curTick + cpu->ticks(delay), true); } void diff --git a/src/arch/mips/regfile/regfile.cc b/src/arch/mips/regfile/regfile.cc index 996c14f14..a1c8eab6a 100644 --- a/src/arch/mips/regfile/regfile.cc +++ b/src/arch/mips/regfile/regfile.cc @@ -193,7 +193,7 @@ RegFile::setNextNPC(Addr val) } void -RegFile::serialize(std::ostream &os) +RegFile::serialize(EventManager *em, std::ostream &os) { intRegFile.serialize(os); //SERIALIZE_ARRAY(floatRegFile, NumFloatRegs); @@ -207,7 +207,8 @@ RegFile::serialize(std::ostream &os) } void -RegFile::unserialize(Checkpoint *cp, const std::string §ion) +RegFile::unserialize(EventManager *em, Checkpoint *cp, + const std::string §ion) { intRegFile.unserialize(cp, section); //UNSERIALIZE_ARRAY(floatRegFile); diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh index 407d9b50a..076cf45f5 100644 --- a/src/arch/mips/regfile/regfile.hh +++ b/src/arch/mips/regfile/regfile.hh @@ -41,8 +41,9 @@ //#include "cpu/base.hh" #include "sim/faults.hh" -class Checkpoint; class BaseCPU; +class Checkpoint; +class EventManager; namespace MipsISA { @@ -99,8 +100,9 @@ namespace MipsISA Addr readNextNPC(); void setNextNPC(Addr val); - void serialize(std::ostream &os); - void unserialize(Checkpoint *cp, const std::string §ion); + void serialize(EventManager *em, std::ostream &os); + void unserialize(EventManager *em, Checkpoint *cp, + const std::string §ion); void changeContext(RegContextParam param, RegContextVal val) { -- cgit v1.2.3 From 94b08bed07d13106381a0bb692bf0d879c5353d4 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Thu, 9 Oct 2008 22:19:39 -0700 Subject: SimObjects: Clean up handling of C++ namespaces. Make them easier to express by only having the cxx_type parameter which has the full namespace name, and drop the cxx_namespace thing. Add support for multiple levels of namespace. --- src/arch/mips/MipsTLB.py | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/MipsTLB.py b/src/arch/mips/MipsTLB.py index 1d0244e22..0054acae5 100644 --- a/src/arch/mips/MipsTLB.py +++ b/src/arch/mips/MipsTLB.py @@ -39,19 +39,16 @@ class MipsTLB(SimObject): class MipsDTB(MipsTLB): type = 'MipsDTB' - cxx_namespace = 'MipsISA' - cxx_class = 'DTB' + cxx_class = 'MipsISA::DTB' size = 64 class MipsITB(MipsTLB): type = 'MipsITB' - cxx_namespace = 'MipsISA' - cxx_class = 'ITB' + cxx_class = 'MipsISA::ITB' size = 64 class MipsUTB(MipsTLB): type = 'MipsUTB' - cxx_namespace = 'MipsISA' - cxx_class = 'UTB' + cxx_class = 'MipsISA::UTB' size = 64 -- cgit v1.2.3 From 8c5dfa453296c5a87a46c409f68e0ef50ebfceb6 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 10 Oct 2008 23:47:42 -0700 Subject: TLB: Make all tlbs derive from a common base class in both python and C++. --- src/arch/mips/MipsTLB.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/MipsTLB.py b/src/arch/mips/MipsTLB.py index 0054acae5..41d46c572 100644 --- a/src/arch/mips/MipsTLB.py +++ b/src/arch/mips/MipsTLB.py @@ -32,7 +32,9 @@ from m5.SimObject import SimObject from m5.params import * -class MipsTLB(SimObject): +from BaseTLB import BaseTLB + +class MipsTLB(BaseTLB): type = 'MipsTLB' abstract = True size = Param.Int("TLB size") -- cgit v1.2.3 From c4f1cc3b482311f878be44259125c9a5b90c0569 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 12 Oct 2008 08:24:09 -0700 Subject: CPU: Eliminate the get_vec function. --- src/arch/mips/interrupts.cc | 12 ------------ src/arch/mips/interrupts.hh | 4 ---- 2 files changed, 16 deletions(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/interrupts.cc b/src/arch/mips/interrupts.cc index c91ee1e99..e04d22631 100755 --- a/src/arch/mips/interrupts.cc +++ b/src/arch/mips/interrupts.cc @@ -156,12 +156,6 @@ static inline void setCauseIP_(ThreadContext *tc, uint8_t val) { return false; } - - uint64_t Interrupts::get_vec(int int_num) - { - panic("MipsISA::Interrupts::get_vec() is not implemented. \n"); - M5_DUMMY_RETURN - } */ void Interrupts::post(int int_num, ThreadContext* tc) { @@ -252,12 +246,6 @@ void Interrupts::updateIntrInfo(ThreadContext *tc) const ; } -uint64_t Interrupts::get_vec(int int_num) -{ - panic("MipsISA::Interrupts::get_vec() is not implemented. \n"); - M5_DUMMY_RETURN - } - bool Interrupts::interruptsPending(ThreadContext *tc) const { //if there is a on cpu timer interrupt (i.e. Compare == Count) diff --git a/src/arch/mips/interrupts.hh b/src/arch/mips/interrupts.hh index f0e928088..99a8f6fa0 100755 --- a/src/arch/mips/interrupts.hh +++ b/src/arch/mips/interrupts.hh @@ -91,8 +91,6 @@ class Interrupts void updateIntrInfoCpuTimerIntr(ThreadContext *tc) const; bool onCpuTimerInterrupt(ThreadContext *tc) const; - uint64_t get_vec(int int_num); - bool check_interrupts(ThreadContext * tc) const{ //return (intstatus != 0) && !(tc->readPC() & 0x3); if (oncputimerintr == false){ @@ -160,8 +158,6 @@ class Interrupts bool interruptsPending(ThreadContext *tc) const; bool onCpuTimerInterrupt(ThreadContext *tc) const; - uint64_t get_vec(int int_num); - bool check_interrupts(ThreadContext * tc) const{ return interruptsPending(tc); } -- cgit v1.2.3 From d9f9c967fbe651e09d444e460a9b1c5a450b1cd2 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 12 Oct 2008 09:09:56 -0700 Subject: Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object. --- src/arch/mips/MipsInterrupts.py | 33 +++++++++++++++++++++++++++++++++ src/arch/mips/SConscript | 1 + 2 files changed, 34 insertions(+) create mode 100644 src/arch/mips/MipsInterrupts.py (limited to 'src/arch/mips') diff --git a/src/arch/mips/MipsInterrupts.py b/src/arch/mips/MipsInterrupts.py new file mode 100644 index 000000000..06cd54263 --- /dev/null +++ b/src/arch/mips/MipsInterrupts.py @@ -0,0 +1,33 @@ +# Copyright (c) 2008 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +from m5.SimObject import SimObject + +class MipsInterrupts(SimObject): + type = 'MipsInterrupts' + cxx_class = 'MipsISA::Interrupts' diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript index 844e7ba15..0368e68bc 100644 --- a/src/arch/mips/SConscript +++ b/src/arch/mips/SConscript @@ -51,6 +51,7 @@ if env['TARGET_ISA'] == 'mips': if env['FULL_SYSTEM']: SimObject('MipsSystem.py') + SimObject('MipsInterrupts.py') Source('idle_event.cc') Source('mips_core_specific.cc') Source('vtophys.cc') -- cgit v1.2.3 From 2736086d7c67a24d9eb87827a22a2b352e342ba2 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 12 Oct 2008 15:59:21 -0700 Subject: CPU: Create a microcode ROM object in the CPU which is defined by the ISA. --- src/arch/mips/microcode_rom.hh | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 src/arch/mips/microcode_rom.hh (limited to 'src/arch/mips') diff --git a/src/arch/mips/microcode_rom.hh b/src/arch/mips/microcode_rom.hh new file mode 100644 index 000000000..a5be81e2a --- /dev/null +++ b/src/arch/mips/microcode_rom.hh @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2008 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_MIPS_MICROCODE_ROM_HH__ +#define __ARCH_MIPS_MICROCODE_ROM_HH__ + +#include "sim/microcode_rom.hh" + +namespace MipsISA +{ + using ::MicrocodeRom; +} + +#endif // __ARCH_MIPS_MICROCODE_ROM_HH__ -- cgit v1.2.3 From f245358343fb26ac976d15b8f2a023caa0f9ba0d Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 12 Oct 2008 17:57:46 -0700 Subject: Get rid of old RegContext code. --- src/arch/mips/regfile.cc | 6 ------ src/arch/mips/regfile/regfile.hh | 4 ---- src/arch/mips/types.hh | 3 --- 3 files changed, 13 deletions(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/regfile.cc b/src/arch/mips/regfile.cc index 0c670af6d..e05bfe2df 100644 --- a/src/arch/mips/regfile.cc +++ b/src/arch/mips/regfile.cc @@ -188,12 +188,6 @@ RegFile::unserialize(Checkpoint *cp, const std::string §ion) } - -void RegFile::changeContext(RegContextParam param, RegContextVal val) -{ - panic("Change Context Not Implemented for MipsISA"); -} - static inline int flattenIntIndex(ThreadContext * tc, int reg) { return reg; diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh index 076cf45f5..ebf793396 100644 --- a/src/arch/mips/regfile/regfile.hh +++ b/src/arch/mips/regfile/regfile.hh @@ -104,10 +104,6 @@ namespace MipsISA void unserialize(EventManager *em, Checkpoint *cp, const std::string §ion); - void changeContext(RegContextParam param, RegContextVal val) - { - } - }; } // namespace MipsISA diff --git a/src/arch/mips/types.hh b/src/arch/mips/types.hh index 4208cb2d8..b459d9e14 100644 --- a/src/arch/mips/types.hh +++ b/src/arch/mips/types.hh @@ -60,9 +60,6 @@ namespace MipsISA MiscReg ctrlreg; } AnyReg; - typedef int RegContextParam; - typedef int RegContextVal; - //used in FP convert & round function enum ConvertType{ SINGLE_TO_DOUBLE, -- cgit v1.2.3 From 9836d81c2bba97e36c43ca22feee1d51a12ce6ac Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Tue, 21 Oct 2008 07:12:53 -0700 Subject: style: Use the correct m5 style for things relating to interrupts. --- src/arch/mips/interrupts.cc | 6 +++--- src/arch/mips/interrupts.hh | 28 +++++++++++++++------------- 2 files changed, 18 insertions(+), 16 deletions(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/interrupts.cc b/src/arch/mips/interrupts.cc index e04d22631..99f96fafc 100755 --- a/src/arch/mips/interrupts.cc +++ b/src/arch/mips/interrupts.cc @@ -76,7 +76,7 @@ static inline void setCauseIP_(ThreadContext *tc, uint8_t val) { intstatus &= ~(1 << int_num); } - void Interrupts::clear_all() + void Interrupts::clearAll() { DPRINTF(Interrupt, "Interrupts all cleared\n"); intstatus = 0; @@ -189,14 +189,14 @@ void Interrupts::clear(int int_num, int index) fatal("Must use Thread COntext when clearing MIPS Interrupts in M5"); } -void Interrupts::clear_all(ThreadContext *tc) +void Interrupts::clearAll(ThreadContext *tc) { DPRINTF(Interrupt, "Interrupts all cleared\n"); uint8_t intstatus = 0; setCauseIP_(tc, intstatus); } -void Interrupts::clear_all() +void Interrupts::clearAll() { fatal("Must use Thread COntext when clearing MIPS Interrupts in M5"); } diff --git a/src/arch/mips/interrupts.hh b/src/arch/mips/interrupts.hh index 99a8f6fa0..af71e4636 100755 --- a/src/arch/mips/interrupts.hh +++ b/src/arch/mips/interrupts.hh @@ -57,23 +57,23 @@ class Interrupts // for posting an interrupt. It sets a bit // in intstatus corresponding to Cause IP*. The // MIPS register Cause is updated by updateIntrInfo - // which is called by check_interrupts + // which is called by checkInterrupts // void post(int int_num, int index); // clear(int int_num, int index) is responsible // for clearing an interrupt. It clear a bit // in intstatus corresponding to Cause IP*. The // MIPS register Cause is updated by updateIntrInfo - // which is called by check_interrupts + // which is called by checkInterrupts // void clear(int int_num, int index); - // clear_all() is responsible + // clearAll() is responsible // for clearing all interrupts. It clears all bits // in intstatus corresponding to Cause IP*. The // MIPS register Cause is updated by updateIntrInfo - // which is called by check_interrupts + // which is called by checkInterrupts // - void clear_all(); + void clearAll(); // getInterrupt(ThreadContext * tc) checks if an interrupt // should be returned. It ands the interrupt mask and @@ -91,7 +91,7 @@ class Interrupts void updateIntrInfoCpuTimerIntr(ThreadContext *tc) const; bool onCpuTimerInterrupt(ThreadContext *tc) const; - bool check_interrupts(ThreadContext * tc) const{ + bool checkInterrupts(ThreadContext *tc) const { //return (intstatus != 0) && !(tc->readPC() & 0x3); if (oncputimerintr == false){ updateIntrInfo(tc); @@ -119,7 +119,7 @@ class Interrupts // for posting an interrupt. It sets a bit // in intstatus corresponding to Cause IP*. The // MIPS register Cause is updated by updateIntrInfo - // which is called by check_interrupts + // which is called by checkInterrupts // void post(int int_num, ThreadContext* tc); void post(int int_num, int index); @@ -128,19 +128,19 @@ class Interrupts // for clearing an interrupt. It clear a bit // in intstatus corresponding to Cause IP*. The // MIPS register Cause is updated by updateIntrInfo - // which is called by check_interrupts + // which is called by checkInterrupts // void clear(int int_num, ThreadContext* tc); void clear(int int_num, int index); - // clear_all() is responsible + // clearAll() is responsible // for clearing all interrupts. It clears all bits // in intstatus corresponding to Cause IP*. The // MIPS register Cause is updated by updateIntrInfo - // which is called by check_interrupts + // which is called by checkInterrupts // - void clear_all(ThreadContext* tc); - void clear_all(); + void clearAll(ThreadContext* tc); + void clearAll(); // getInterrupt(ThreadContext * tc) checks if an interrupt // should be returned. It ands the interrupt mask and @@ -158,7 +158,9 @@ class Interrupts bool interruptsPending(ThreadContext *tc) const; bool onCpuTimerInterrupt(ThreadContext *tc) const; - bool check_interrupts(ThreadContext * tc) const{ + bool + checkInterrupts(ThreadContext *tc) const + { return interruptsPending(tc); } -- cgit v1.2.3 From c55a467a06eaa59c47c52a2adddc266b8e545589 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Sun, 2 Nov 2008 21:56:57 -0500 Subject: make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch. --- src/arch/mips/locked_mem.hh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh index 07dc9d588..5877b1439 100644 --- a/src/arch/mips/locked_mem.hh +++ b/src/arch/mips/locked_mem.hh @@ -85,7 +85,7 @@ handleLockedWrite(XC *xc, Request *req) if (stCondFailures % 10 == 0) { warn("%i: cpu %d: %d consecutive " "store conditional failures\n", - curTick, xc->readCpuId(), stCondFailures); + curTick, xc->cpuId(), stCondFailures); } if (stCondFailures == 5000) { -- cgit v1.2.3 From d857faf073895dcfde97141bd6346fe5d4317f8e Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Sun, 2 Nov 2008 21:57:07 -0500 Subject: Add in Context IDs to the simulator. From now on, cpuId is almost never used, the primary identifier for a hardware context should be contextId(). The concept of threads within a CPU remains, in the form of threadId() because sometimes you need to know which context within a cpu to manipulate. --- src/arch/mips/locked_mem.hh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh index 5877b1439..9f41ba075 100644 --- a/src/arch/mips/locked_mem.hh +++ b/src/arch/mips/locked_mem.hh @@ -83,9 +83,9 @@ handleLockedWrite(XC *xc, Request *req) stCondFailures++; xc->setStCondFailures(stCondFailures); if (stCondFailures % 10 == 0) { - warn("%i: cpu %d: %d consecutive " + warn("%i: context %d: %d consecutive " "store conditional failures\n", - curTick, xc->cpuId(), stCondFailures); + curTick, xc->contextId(), stCondFailures); } if (stCondFailures == 5000) { -- cgit v1.2.3 From dd99ff23c6a71f7173014b5008d0cf12b7ef223a Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Tue, 4 Nov 2008 11:35:42 -0500 Subject: get rid of all instances of readTid() and getThreadNum(). Unify and eliminate redundancies with threadId() as their replacement. --- src/arch/mips/isa/formats/mt.isa | 4 ++-- src/arch/mips/locked_mem.hh | 6 +++--- src/arch/mips/mt.hh | 8 ++++---- src/arch/mips/utility.cc | 2 +- 4 files changed, 10 insertions(+), 10 deletions(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa index 81fdc2898..1928ee903 100644 --- a/src/arch/mips/isa/formats/mt.isa +++ b/src/arch/mips/isa/formats/mt.isa @@ -196,7 +196,7 @@ def format MT_Control(code, *opt_flags) {{ def format MT_MFTR(code, *flags) {{ flags += ('IsNonSpeculative', ) -# code = 'std::cerr << curTick << \": T\" << xc->tcBase()->getThreadNum() << \": Executing MT INST: ' + name + '\" << endl;\n' + code +# code = 'std::cerr << curTick << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code code += 'if (MT_H == 1) {\n' code += 'data = bits(data, top_bit, bottom_bit);\n' @@ -212,7 +212,7 @@ def format MT_MFTR(code, *flags) {{ def format MT_MTTR(code, *flags) {{ flags += ('IsNonSpeculative', ) -# code = 'std::cerr << curTick << \": T\" << xc->tcBase()->getThreadNum() << \": Executing MT INST: ' + name + '\" << endl;\n' + code +# code = 'std::cerr << curTick << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code iop = InstObjParams(name, Name, 'MTOp', code, flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh index 9f41ba075..021b8cf73 100644 --- a/src/arch/mips/locked_mem.hh +++ b/src/arch/mips/locked_mem.hh @@ -52,7 +52,7 @@ handleLockedRead(XC *xc, Request *req) xc->setMiscRegNoEffect(LLAddr, req->getPaddr() & ~0xf); xc->setMiscRegNoEffect(LLFlag, true); DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link Address set to %x.\n", - req->getThreadNum(), req->getPaddr() & ~0xf); + req->threadId(), req->getPaddr() & ~0xf); } @@ -94,10 +94,10 @@ handleLockedWrite(XC *xc, Request *req) if (!lock_flag){ DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, Store Conditional Failed.\n", - req->getThreadNum()); + req->threadId()); } else if ((req->getPaddr() & ~0xf) != lock_addr) { DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, Store Conditional Failed.\n", - req->getThreadNum()); + req->threadId()); } // store conditional failed already, so don't issue it to mem return false; diff --git a/src/arch/mips/mt.hh b/src/arch/mips/mt.hh index 20658df28..8828a09a5 100755 --- a/src/arch/mips/mt.hh +++ b/src/arch/mips/mt.hh @@ -78,7 +78,7 @@ haltThread(TC *tc) // @TODO: Needs to check if this is a branch and if so, take previous instruction tc->setMiscReg(TCRestart, tc->readNextPC()); - warn("%i: Halting thread %i in %s @ PC %x, setting restart PC to %x", curTick, tc->getThreadNum(), tc->getCpuPtr()->name(), + warn("%i: Halting thread %i in %s @ PC %x, setting restart PC to %x", curTick, tc->threadId(), tc->getCpuPtr()->name(), tc->readPC(), tc->readNextPC()); } } @@ -98,7 +98,7 @@ restoreThread(TC *tc) tc->setNextNPC(pc + 8); tc->activate(0); - warn("%i: Restoring thread %i in %s @ PC %x", curTick, tc->getThreadNum(), tc->getCpuPtr()->name(), + warn("%i: Restoring thread %i in %s @ PC %x", curTick, tc->threadId(), tc->getCpuPtr()->name(), tc->readPC()); } } @@ -217,7 +217,7 @@ yieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask) if (ok == 1) { unsigned tcstatus = tc->readMiscRegNoEffect(TCStatus); tc->setMiscReg(TCStatus, insertBits(tcstatus, TCS_A, TCS_A, 0)); - warn("%i: Deactivating Hardware Thread Context #%i", curTick, tc->getThreadNum()); + warn("%i: Deactivating Hardware Thread Context #%i", curTick, tc->threadId()); } } else if (src_reg > 0) { if (src_reg && !yield_mask != 0) { @@ -238,7 +238,7 @@ yieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask) fault = new ThreadFault(); } else { //tc->ScheduleOtherThreads(); - //std::cerr << "T" << tc->getThreadNum() << "YIELD: Schedule Other Threads.\n" << std::endl; + //std::cerr << "T" << tc->threadId() << "YIELD: Schedule Other Threads.\n" << std::endl; //tc->suspend(); // Save last known PC in TCRestart // @TODO: Needs to check if this is a branch and if so, take previous instruction diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc index 1985c0f43..5908caf68 100644 --- a/src/arch/mips/utility.cc +++ b/src/arch/mips/utility.cc @@ -259,7 +259,7 @@ zeroRegisters(CPU *cpu) void startupCPU(ThreadContext *tc, int cpuId) { - tc->activate(0/*tc->getThreadNum()*/); + tc->activate(0/*tc->threadId()*/); } } // namespace MipsISA -- cgit v1.2.3 From 9c49bc7b00aa24b0488a83039ae8762d8f8094c5 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Mon, 10 Nov 2008 11:51:17 -0800 Subject: mem: update stuff for changes to Packet and Request --- src/arch/mips/isa/formats/mem.isa | 6 +++--- src/arch/mips/isa/formats/util.isa | 3 ++- src/arch/mips/tlb.cc | 2 +- 3 files changed, 6 insertions(+), 5 deletions(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa index f0210c29b..8596308e2 100644 --- a/src/arch/mips/isa/formats/mem.isa +++ b/src/arch/mips/isa/formats/mem.isa @@ -43,7 +43,7 @@ output header {{ protected: /// Memory request flags. See mem_req_base.hh. - unsigned memAccessFlags; + Request::Flags memAccessFlags; /// Pointer to EAComp object. const StaticInstPtr eaCompPtr; /// Pointer to MemAcc object. @@ -57,7 +57,7 @@ output header {{ StaticInstPtr _eaCompPtr = nullStaticInstPtr, StaticInstPtr _memAccPtr = nullStaticInstPtr) : MipsStaticInst(mnem, _machInst, __opClass), - memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr), + eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr), disp(sext<16>(OFFSET)) { } @@ -70,7 +70,7 @@ output header {{ const StaticInstPtr &eaCompInst() const { return eaCompPtr; } const StaticInstPtr &memAccInst() const { return memAccPtr; } - unsigned memAccFlags() { return memAccessFlags; } + Request::Flags memAccFlags() { return memAccessFlags; } }; /** diff --git a/src/arch/mips/isa/formats/util.isa b/src/arch/mips/isa/formats/util.isa index 0405aa5b3..786a964d4 100644 --- a/src/arch/mips/isa/formats/util.isa +++ b/src/arch/mips/isa/formats/util.isa @@ -61,7 +61,8 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, inst_flags) if mem_flags: - s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';' + mem_flags = [ 'Request::%s' % flag for flag in mem_flags ] + s = '\n\tmemAccessFlags.reset(' + string.join(mem_flags, '|') + ');' iop.constructor += s memacc_iop.constructor += s diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc index 7c3b6aed5..e91da4eea 100644 --- a/src/arch/mips/tlb.cc +++ b/src/arch/mips/tlb.cc @@ -149,7 +149,7 @@ TLB::checkCacheability(RequestPtr &req) // or by the TLB entry if((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) { // mark request as uncacheable - req->setFlags(req->getFlags() | UNCACHEABLE); + req->setFlags(Request::UNCACHEABLE); } return NoFault; } -- cgit v1.2.3 From 5711282f87afb609c79d657ed6aa8c9259b5b827 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Fri, 14 Nov 2008 04:55:30 -0800 Subject: Fix a bunch of bugs I introduced when I changed the flags stuff for packets. I did some of the flags and assertions wrong. Thanks to Brad Beckmann for pointing this out. I should have run the opt regressions instead of the fast. I also screwed up some of the logical functions in the Flags class. --- src/arch/mips/isa/formats/util.isa | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/isa/formats/util.isa b/src/arch/mips/isa/formats/util.isa index 786a964d4..f729cbf63 100644 --- a/src/arch/mips/isa/formats/util.isa +++ b/src/arch/mips/isa/formats/util.isa @@ -62,7 +62,7 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, if mem_flags: mem_flags = [ 'Request::%s' % flag for flag in mem_flags ] - s = '\n\tmemAccessFlags.reset(' + string.join(mem_flags, '|') + ');' + s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';' iop.constructor += s memacc_iop.constructor += s -- cgit v1.2.3 From 4514f565e3dfe1de41bbaec05f3f0074e5299bac Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sat, 15 Nov 2008 09:30:10 -0800 Subject: syscalls: fix latent brk/obreak bug. Bogus calls to ChunkGenerator with negative size were triggering a new assertion that was added there. Also did a little renaming and cleanup in the process. --- src/arch/mips/linux/process.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/linux/process.cc b/src/arch/mips/linux/process.cc index 8a13d0f18..56413484b 100644 --- a/src/arch/mips/linux/process.cc +++ b/src/arch/mips/linux/process.cc @@ -138,7 +138,7 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = { /* 14 */ SyscallDesc("mknod", unimplementedFunc), /* 15 */ SyscallDesc("chmod", chmodFunc), /* 16 */ SyscallDesc("lchown", chownFunc), - /* 17 */ SyscallDesc("break", obreakFunc), + /* 17 */ SyscallDesc("break", brkFunc), /* 18 */ SyscallDesc("unused#18", unimplementedFunc), /* 19 */ SyscallDesc("lseek", lseekFunc), /* 20 */ SyscallDesc("getpid", getpidFunc), @@ -166,7 +166,7 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = { /* 42 */ SyscallDesc("pipe", pipePseudoFunc), /* 43 */ SyscallDesc("times", unimplementedFunc), /* 44 */ SyscallDesc("prof", unimplementedFunc), - /* 45 */ SyscallDesc("brk", obreakFunc), + /* 45 */ SyscallDesc("brk", brkFunc), /* 46 */ SyscallDesc("setgid", unimplementedFunc), /* 47 */ SyscallDesc("getgid", getgidFunc), /* 48 */ SyscallDesc("signal", ignoreFunc), -- cgit v1.2.3 From 8153790d0004439f8e9d473da97699644234117b Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Tue, 13 Jan 2009 14:17:50 -0800 Subject: SCons: centralize the Dir() workaround for newer versions of scons. Scons bug id: 2006 M5 Bug id: 308 --- src/arch/mips/SConscript | 3 --- 1 file changed, 3 deletions(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript index 0368e68bc..0b470def6 100644 --- a/src/arch/mips/SConscript +++ b/src/arch/mips/SConscript @@ -33,9 +33,6 @@ Import('*') if env['TARGET_ISA'] == 'mips': -# Workaround for bug in SCons version > 0.97d20071212 -# Scons bug id: 2006 M5 Bug id: 308 - Dir('isa/formats') Source('faults.cc') Source('regfile/int_regfile.cc') Source('regfile/float_regfile.cc') -- cgit v1.2.3 From 36d9065f5f716f88c82a3f4e9a75fa040039aa0a Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Tue, 10 Feb 2009 15:49:29 -0800 Subject: syscall: Expose ioctl for MIPS --- src/arch/mips/linux/linux.hh | 18 +++++++++--------- src/arch/mips/linux/process.cc | 2 +- 2 files changed, 10 insertions(+), 10 deletions(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/linux/linux.hh b/src/arch/mips/linux/linux.hh index 0d71a3c58..4667748fb 100644 --- a/src/arch/mips/linux/linux.hh +++ b/src/arch/mips/linux/linux.hh @@ -94,15 +94,15 @@ class MipsLinux : public Linux //@{ /// ioctl() command codes. - static const unsigned TIOCGETP = 0x7408; - static const unsigned TIOCSETP = 0x7409; - static const unsigned TIOCSETN = 0x740a; - static const unsigned TIOCSETC = 0x7411; - static const unsigned TIOCGETC = 0x7412; - static const unsigned FIONREAD = 0x467f; - static const unsigned TIOCISATTY = 0x5480; - static const unsigned TIOCGETS = 0x540d; - static const unsigned TIOCGETA = 0x7417; + static const unsigned TIOCGETP_ = 0x7408; + static const unsigned TIOCSETP_ = 0x7409; + static const unsigned TIOCSETN_ = 0x740a; + static const unsigned TIOCSETC_ = 0x7411; + static const unsigned TIOCGETC_ = 0x7412; + static const unsigned FIONREAD_ = 0x467f; + static const unsigned TIOCISATTY_ = 0x5480; + static const unsigned TIOCGETS_ = 0x540d; + static const unsigned TIOCGETA_ = 0x7417; //@} /// For table(). diff --git a/src/arch/mips/linux/process.cc b/src/arch/mips/linux/process.cc index 56413484b..ce09e1628 100644 --- a/src/arch/mips/linux/process.cc +++ b/src/arch/mips/linux/process.cc @@ -175,7 +175,7 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = { /* 51 */ SyscallDesc("acct", unimplementedFunc), /* 52 */ SyscallDesc("umount2", unimplementedFunc), /* 53 */ SyscallDesc("lock", unimplementedFunc), - /* 54 */ SyscallDesc("ioctl", unimplementedFunc/*ioctlFunc*/), + /* 54 */ SyscallDesc("ioctl", ioctlFunc), /* 55 */ SyscallDesc("fcntl", fcntlFunc), /* 56 */ SyscallDesc("mpx", unimplementedFunc), /* 57 */ SyscallDesc("setpgid", unimplementedFunc), -- cgit v1.2.3 From 5d029ff11e88ba0ab89c88e500c5d0d2edaf744e Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Mon, 16 Feb 2009 17:47:39 -0500 Subject: sycalls: implement mremap() and add DATA flag for getrlimit(). mremap has been tested on Alpha, compiles for the rest but not tested. I don't see why it wouldn't work though. --- src/arch/mips/linux/process.cc | 2 +- src/arch/mips/tlb.hh | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/linux/process.cc b/src/arch/mips/linux/process.cc index ce09e1628..9d9d33325 100644 --- a/src/arch/mips/linux/process.cc +++ b/src/arch/mips/linux/process.cc @@ -288,7 +288,7 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = { /* 164 */ SyscallDesc("sched_get_priority_min", unimplementedFunc), /* 165 */ SyscallDesc("sched_rr_get_interval", unimplementedFunc), /* 166 */ SyscallDesc("nanosleep", unimplementedFunc), - /* 167 */ SyscallDesc("mremap", unimplementedFunc), + /* 167 */ SyscallDesc("mremap", mremapFunc), /* 168 */ SyscallDesc("accept", unimplementedFunc), /* 169 */ SyscallDesc("bind", unimplementedFunc), /* 170 */ SyscallDesc("connect", unimplementedFunc), diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh index feb2509c5..4a8fc32ac 100644 --- a/src/arch/mips/tlb.hh +++ b/src/arch/mips/tlb.hh @@ -68,6 +68,9 @@ struct TlbEntry return _pageStart; } + void + updateVaddr(Addr new_vaddr) {} + void serialize(std::ostream &os) { SERIALIZE_SCALAR(_pageStart); -- cgit v1.2.3 From 6c5afe6346b31edf6af245002c270a3c26618833 Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Fri, 20 Feb 2009 11:02:48 -0500 Subject: Remove unnecessary building of FreeList/RenameMap in InOrder. Clean-up comments and O3 extensions InOrder Thread Context --- src/arch/mips/regfile.cc | 6 ------ 1 file changed, 6 deletions(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/regfile.cc b/src/arch/mips/regfile.cc index e05bfe2df..663115bb6 100644 --- a/src/arch/mips/regfile.cc +++ b/src/arch/mips/regfile.cc @@ -199,12 +199,6 @@ MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest) panic("Copy Regs Not Implemented Yet\n"); } -void -MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest); -{ - panic("Copy Regs Not Implemented Yet\n"); -} - void MipsISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest) { -- cgit v1.2.3 From 5605079b1f20bc7f6a4a80c8d1e4daabe7125270 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 25 Feb 2009 10:15:44 -0800 Subject: ISA: Replace the translate functions in the TLBs with translateAtomic. --- src/arch/mips/tlb.cc | 4 ++-- src/arch/mips/tlb.hh | 5 +++-- 2 files changed, 5 insertions(+), 4 deletions(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc index e91da4eea..db21c7919 100644 --- a/src/arch/mips/tlb.cc +++ b/src/arch/mips/tlb.cc @@ -310,7 +310,7 @@ TLB::regStats() } Fault -ITB::translate(RequestPtr &req, ThreadContext *tc) +ITB::translateAtomic(RequestPtr &req, ThreadContext *tc) { #if !FULL_SYSTEM Process * p = tc->getProcessPtr(); @@ -427,7 +427,7 @@ ITB::translate(RequestPtr &req, ThreadContext *tc) } Fault -DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) +DTB::translateAtomic(RequestPtr &req, ThreadContext *tc, bool write) { #if !FULL_SYSTEM Process * p = tc->getProcessPtr(); diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh index 4a8fc32ac..acb393116 100644 --- a/src/arch/mips/tlb.hh +++ b/src/arch/mips/tlb.hh @@ -145,7 +145,7 @@ class ITB : public TLB { typedef MipsTLBParams Params; ITB(const Params *p); - Fault translate(RequestPtr &req, ThreadContext *tc); + Fault translateAtomic(RequestPtr &req, ThreadContext *tc); }; class DTB : public TLB { @@ -153,7 +153,8 @@ class DTB : public TLB { typedef MipsTLBParams Params; DTB(const Params *p); - Fault translate(RequestPtr &req, ThreadContext *tc, bool write = false); + Fault translateAtomic(RequestPtr &req, ThreadContext *tc, + bool write = false); }; class UTB : public ITB, public DTB { -- cgit v1.2.3 From 6ed47e94644f854baa33d1e9f367cc9eebd99abf Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 25 Feb 2009 10:16:15 -0800 Subject: CPU: Implement translateTiming which defers to translateAtomic, and convert the timing simple CPU to use it. --- src/arch/mips/tlb.cc | 20 ++++++++++++++++++-- src/arch/mips/tlb.hh | 8 ++++++-- 2 files changed, 24 insertions(+), 4 deletions(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc index db21c7919..eac44eba8 100644 --- a/src/arch/mips/tlb.cc +++ b/src/arch/mips/tlb.cc @@ -310,7 +310,7 @@ TLB::regStats() } Fault -ITB::translateAtomic(RequestPtr &req, ThreadContext *tc) +ITB::translateAtomic(RequestPtr req, ThreadContext *tc) { #if !FULL_SYSTEM Process * p = tc->getProcessPtr(); @@ -426,8 +426,16 @@ ITB::translateAtomic(RequestPtr &req, ThreadContext *tc) #endif } +void +ITB::translateTiming(RequestPtr req, ThreadContext *tc, + Translation *translation) +{ + assert(translation); + translation->finish(translateAtomic(req, tc), req, tc, false); +} + Fault -DTB::translateAtomic(RequestPtr &req, ThreadContext *tc, bool write) +DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write) { #if !FULL_SYSTEM Process * p = tc->getProcessPtr(); @@ -564,6 +572,14 @@ DTB::translateAtomic(RequestPtr &req, ThreadContext *tc, bool write) #endif } +void +DTB::translateTiming(RequestPtr req, ThreadContext *tc, + Translation *translation, bool write) +{ + assert(translation); + translation->finish(translateAtomic(req, tc, write), req, tc, write); +} + /////////////////////////////////////////////////////////////////////// // // Mips ITB diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh index acb393116..1ab9d77e5 100644 --- a/src/arch/mips/tlb.hh +++ b/src/arch/mips/tlb.hh @@ -145,7 +145,9 @@ class ITB : public TLB { typedef MipsTLBParams Params; ITB(const Params *p); - Fault translateAtomic(RequestPtr &req, ThreadContext *tc); + Fault translateAtomic(RequestPtr req, ThreadContext *tc); + void translateTiming(RequestPtr req, ThreadContext *tc, + Translation *translation); }; class DTB : public TLB { @@ -153,8 +155,10 @@ class DTB : public TLB { typedef MipsTLBParams Params; DTB(const Params *p); - Fault translateAtomic(RequestPtr &req, ThreadContext *tc, + Fault translateAtomic(RequestPtr req, ThreadContext *tc, bool write = false); + void translateTiming(RequestPtr req, ThreadContext *tc, + Translation *translation, bool write = false); }; class UTB : public ITB, public DTB { -- cgit v1.2.3 From 437b02884dedccc6f72f3e5d9c05d3a2dd6c6a2d Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 25 Feb 2009 10:22:31 -0800 Subject: ISA: Get rid of the get*RegName functions. --- src/arch/mips/regfile/float_regfile.hh | 5 ----- src/arch/mips/regfile/int_regfile.hh | 5 ----- src/arch/mips/regfile/misc_regfile.cc | 16 +++++----------- src/arch/mips/regfile/misc_regfile.hh | 2 -- 4 files changed, 5 insertions(+), 23 deletions(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/regfile/float_regfile.hh b/src/arch/mips/regfile/float_regfile.hh index 1537855df..0c0ecc7eb 100644 --- a/src/arch/mips/regfile/float_regfile.hh +++ b/src/arch/mips/regfile/float_regfile.hh @@ -44,11 +44,6 @@ class Checkpoint; namespace MipsISA { - static inline std::string getFloatRegName(RegIndex) - { - return ""; - } - const uint32_t MIPS32_QNAN = 0x7fbfffff; const uint64_t MIPS64_QNAN = ULL(0x7fbfffffffffffff); diff --git a/src/arch/mips/regfile/int_regfile.hh b/src/arch/mips/regfile/int_regfile.hh index 0f453a382..c5a6bb345 100644 --- a/src/arch/mips/regfile/int_regfile.hh +++ b/src/arch/mips/regfile/int_regfile.hh @@ -42,11 +42,6 @@ class Checkpoint; namespace MipsISA { - static inline std::string getIntRegName(RegIndex) - { - return ""; - } - enum MiscIntRegNums { LO = NumIntArchRegs, HI, diff --git a/src/arch/mips/regfile/misc_regfile.cc b/src/arch/mips/regfile/misc_regfile.cc index 08487db90..ea858abf0 100644 --- a/src/arch/mips/regfile/misc_regfile.cc +++ b/src/arch/mips/regfile/misc_regfile.cc @@ -437,12 +437,6 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads, } -inline std::string -MipsISA::getMiscRegName(unsigned reg_idx) -{ - return MiscRegFile::miscRegNames[reg_idx]; -} - inline unsigned MiscRegFile::getVPENum(unsigned tid) { @@ -457,7 +451,7 @@ MiscRegFile::readRegNoEffect(int reg_idx, unsigned tid) unsigned reg_sel = (bankType[misc_reg] == perThreadContext) ? tid : getVPENum(tid); DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) (%lx).\n", - misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg), + misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], miscRegFile[misc_reg][reg_sel]); return miscRegFile[misc_reg][reg_sel]; } @@ -474,7 +468,7 @@ MiscRegFile::readReg(int reg_idx, ? tid : getVPENum(tid); DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n", - misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg), + misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], miscRegFile[misc_reg][reg_sel]); @@ -494,7 +488,7 @@ MiscRegFile::setRegNoEffect(int reg_idx, const MiscReg &val, unsigned tid) DPRINTF(MipsPRA, "[tid:%i]: Setting (direct set) CP0 Register:%u " "Select:%u (%s) to %#x.\n", - tid, misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg), val); + tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val); miscRegFile[misc_reg][reg_sel] = val; } @@ -507,7 +501,7 @@ MiscRegFile::setRegMask(int reg_idx, const MiscReg &val, unsigned tid) ? tid : getVPENum(tid); DPRINTF(MipsPRA, "[tid:%i]: Setting CP0 Register: %u Select: %u (%s) to %#x\n", - tid, misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg), val); + tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val); miscRegFile_WriteMask[misc_reg][reg_sel] = val; } @@ -527,7 +521,7 @@ MiscRegFile::setReg(int reg_idx, const MiscReg &val, DPRINTF(MipsPRA, "[tid:%i]: Setting CP0 Register:%u " "Select:%u (%s) to %#x, with effect.\n", - tid, misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg), val); + tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val); MiscReg cp0_val = filterCP0Write(misc_reg, reg_sel, val); diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh index 4bec9a49e..c611d94cc 100644 --- a/src/arch/mips/regfile/misc_regfile.hh +++ b/src/arch/mips/regfile/misc_regfile.hh @@ -162,8 +162,6 @@ namespace MipsISA static std::string miscRegNames[NumMiscRegs]; }; - - inline std::string getMiscRegName(unsigned reg_idx); } // namespace MipsISA #endif -- cgit v1.2.3 From 9a000c51736d97c1109be296ea7d1fd41d84debb Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 27 Feb 2009 09:22:14 -0800 Subject: Processes: Make getting and setting system call arguments part of a process object. --- src/arch/mips/isa_traits.hh | 14 +---------- src/arch/mips/linux/process.cc | 14 +++++------ src/arch/mips/process.cc | 34 ++++++++++++++++++++++++++ src/arch/mips/process.hh | 4 +++ src/arch/mips/syscallreturn.hh | 55 ------------------------------------------ 5 files changed, 46 insertions(+), 75 deletions(-) delete mode 100644 src/arch/mips/syscallreturn.hh (limited to 'src/arch/mips') diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh index 3450c273e..ed4ed9877 100644 --- a/src/arch/mips/isa_traits.hh +++ b/src/arch/mips/isa_traits.hh @@ -190,13 +190,6 @@ namespace MipsISA // semantically meaningful register indices const int ZeroReg = 0; const int AssemblerReg = 1; - const int ReturnValueReg = 2; - const int ReturnValueReg1 = 2; - const int ReturnValueReg2 = 3; - const int ArgumentReg0 = 4; - const int ArgumentReg1 = 5; - const int ArgumentReg2 = 6; - const int ArgumentReg3 = 7; const int KernelReg0 = 26; const int KernelReg1 = 27; const int GlobalPointerReg = 28; @@ -204,12 +197,7 @@ namespace MipsISA const int FramePointerReg = 30; const int ReturnAddressReg = 31; - const int ArgumentReg[] = {4, 5, 6, 7}; - const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int); - - const int SyscallNumReg = ReturnValueReg1; - const int SyscallPseudoReturnReg = ReturnValueReg2; - const int SyscallSuccessReg = ArgumentReg3; + const int SyscallPseudoReturnReg = 3; const int LogVMPageSize = 13; // 8K bytes const int VMPageSize = (1 << LogVMPageSize); diff --git a/src/arch/mips/linux/process.cc b/src/arch/mips/linux/process.cc index 9d9d33325..dc3b84ced 100644 --- a/src/arch/mips/linux/process.cc +++ b/src/arch/mips/linux/process.cc @@ -51,7 +51,7 @@ static SyscallReturn unameFunc(SyscallDesc *desc, int callnum, LiveProcess *process, ThreadContext *tc) { - TypedBufferArg name(tc->getSyscallArg(0)); + TypedBufferArg name(process->getSyscallArg(tc, 0)); strcpy(name->sysname, "Linux"); strcpy(name->nodename,"m5.eecs.umich.edu"); @@ -70,13 +70,13 @@ static SyscallReturn sys_getsysinfoFunc(SyscallDesc *desc, int callnum, LiveProcess *process, ThreadContext *tc) { - unsigned op = tc->getSyscallArg(0); - // unsigned nbytes = tc->getSyscallArg(2); + unsigned op = process->getSyscallArg(tc, 0); + // unsigned nbytes = process->getSyscallArg(tc, 2); switch (op) { case 45: { // GSI_IEEE_FP_CONTROL - TypedBufferArg fpcr(tc->getSyscallArg(1)); + TypedBufferArg fpcr(process->getSyscallArg(tc, 1)); // I don't think this exactly matches the HW FPCR *fpcr = 0; fpcr.copyOut(tc->getMemPort()); @@ -97,13 +97,13 @@ static SyscallReturn sys_setsysinfoFunc(SyscallDesc *desc, int callnum, LiveProcess *process, ThreadContext *tc) { - unsigned op = tc->getSyscallArg(0); - // unsigned nbytes = tc->getSyscallArg(2); + unsigned op = process->getSyscallArg(tc, 0); + // unsigned nbytes = process->getSyscallArg(tc, 2); switch (op) { case 14: { // SSI_IEEE_FP_CONTROL - TypedBufferArg fpcr(tc->getSyscallArg(1)); + TypedBufferArg fpcr(process->getSyscallArg(tc, 1)); // I don't think this exactly matches the HW FPCR fpcr.copyIn(tc->getMemPort()); DPRINTFR(SyscallVerbose, "sys_setsysinfo(SSI_IEEE_FP_CONTROL): " diff --git a/src/arch/mips/process.cc b/src/arch/mips/process.cc index b7bd22d78..784ddfe33 100644 --- a/src/arch/mips/process.cc +++ b/src/arch/mips/process.cc @@ -40,6 +40,10 @@ using namespace std; using namespace MipsISA; +static const int SyscallSuccessReg = 7; +static const int FirstArgumentReg = 4; +static const int ReturnValueReg = 2; + MipsLiveProcess::MipsLiveProcess(LiveProcessParams * params, ObjectFile *objFile) : LiveProcess(params, objFile) @@ -64,3 +68,33 @@ MipsLiveProcess::startup() { argsInit(MachineBytes, VMPageSize); } + +MipsISA::IntReg +MipsLiveProcess::getSyscallArg(ThreadContext *tc, int i) +{ + assert(i < 6); + return tc->readIntReg(FirstArgumentReg + i); +} + +void +MipsLiveProcess::setSyscallArg(ThreadContext *tc, + int i, MipsISA::IntReg val) +{ + assert(i < 6); + tc->setIntReg(FirstArgumentReg + i, val); +} + +void +MipsLiveProcess::setSyscallReturn(ThreadContext *tc, + SyscallReturn return_value) +{ + if (return_value.successful()) { + // no error + tc->setIntReg(SyscallSuccessReg, 0); + tc->setIntReg(ReturnValueReg, return_value.value()); + } else { + // got an error, return details + tc->setIntReg(SyscallSuccessReg, (IntReg) -1); + tc->setIntReg(ReturnValueReg, -return_value.value()); + } +} diff --git a/src/arch/mips/process.hh b/src/arch/mips/process.hh index 18bf289b8..87c62330f 100644 --- a/src/arch/mips/process.hh +++ b/src/arch/mips/process.hh @@ -47,6 +47,10 @@ class MipsLiveProcess : public LiveProcess virtual void startup(); + public: + MipsISA::IntReg getSyscallArg(ThreadContext *tc, int i); + void setSyscallArg(ThreadContext *tc, int i, MipsISA::IntReg val); + void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value); }; diff --git a/src/arch/mips/syscallreturn.hh b/src/arch/mips/syscallreturn.hh deleted file mode 100644 index 24a40ddcc..000000000 --- a/src/arch/mips/syscallreturn.hh +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2007 MIPS Technologies, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - * Korey Sewell - */ - -#ifndef __ARCH_MIPS_SYSCALLRETURN_HH__ -#define __ARCH_MIPS_SYSCALLRETURN_HH__ - -#include "sim/syscallreturn.hh" -#include "cpu/thread_context.hh" - -namespace MipsISA -{ - static inline void setSyscallReturn(SyscallReturn return_value, - ThreadContext *tc) - { - if (return_value.successful()) { - // no error - tc->setIntReg(SyscallSuccessReg, 0); - tc->setIntReg(ReturnValueReg1, return_value.value()); - } else { - // got an error, return details - tc->setIntReg(SyscallSuccessReg, (IntReg) -1); - tc->setIntReg(ReturnValueReg1, -return_value.value()); - } - } -} - -#endif -- cgit v1.2.3 From 307905095caaa277e8ccbd58f095381d79b0c402 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sat, 28 Feb 2009 20:14:22 -0500 Subject: Fix Num_Syscall_Descs check bug in non-x86 ISAs. (See cset d35d2b28df38 for x86 fix.) --- src/arch/mips/linux/process.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/linux/process.cc b/src/arch/mips/linux/process.cc index dc3b84ced..24e71305a 100644 --- a/src/arch/mips/linux/process.cc +++ b/src/arch/mips/linux/process.cc @@ -425,7 +425,7 @@ MipsLinuxProcess::getDesc(int callnum) //MIPS32 syscalls are in the range of 4000 - 4999 int m5_sys_idx = callnum - 4000; - if (m5_sys_idx < 0 || m5_sys_idx > Num_Syscall_Descs) + if (m5_sys_idx < 0 || m5_sys_idx >= Num_Syscall_Descs) return NULL; return &syscallDescs[m5_sys_idx]; -- cgit v1.2.3 From e3d6e8882e02d607ed69108d4bc1301de9c2de56 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Thu, 5 Mar 2009 17:15:31 -0800 Subject: Get rid of 'using namespace' declarations in headers. --- src/arch/mips/bare_iron/system.hh | 2 -- src/arch/mips/isa_traits.hh | 2 -- src/arch/mips/linux/linux.hh | 3 --- src/arch/mips/linux/system.hh | 5 +---- src/arch/mips/mt.hh | 3 +-- src/arch/mips/regfile/misc_regfile.cc | 1 + 6 files changed, 3 insertions(+), 13 deletions(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/bare_iron/system.hh b/src/arch/mips/bare_iron/system.hh index ab4e02344..e593f832c 100755 --- a/src/arch/mips/bare_iron/system.hh +++ b/src/arch/mips/bare_iron/system.hh @@ -39,8 +39,6 @@ class IdleStartEvent; #include "arch/mips/system.hh" #include "params/BareIronMipsSystem.hh" -using namespace MipsISA; - /** * This class contains linux specific system code (Loading, Events). * It points to objects that are the system binaries to load and patches them diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh index ed4ed9877..12c887132 100644 --- a/src/arch/mips/isa_traits.hh +++ b/src/arch/mips/isa_traits.hh @@ -381,6 +381,4 @@ namespace MipsISA }; -using namespace MipsISA; - #endif // __ARCH_MIPS_ISA_TRAITS_HH__ diff --git a/src/arch/mips/linux/linux.hh b/src/arch/mips/linux/linux.hh index 4667748fb..aaeba0a42 100644 --- a/src/arch/mips/linux/linux.hh +++ b/src/arch/mips/linux/linux.hh @@ -32,9 +32,6 @@ #define __ARCH_MIPS_LINUX_LINUX_HH__ #include "kern/linux/linux.hh" -#include - -using std::string; class MipsLinux : public Linux { diff --git a/src/arch/mips/linux/system.hh b/src/arch/mips/linux/system.hh index 24fb604ed..984f74694 100644 --- a/src/arch/mips/linux/system.hh +++ b/src/arch/mips/linux/system.hh @@ -43,9 +43,6 @@ class IdleStartEvent; #include "kern/linux/events.hh" #include "params/LinuxMipsSystem.hh" -using namespace MipsISA; -using namespace Linux; - /** * This class contains linux specific system code (Loading, Events). * It points to objects that are the system binaries to load and patches them @@ -112,7 +109,7 @@ class LinuxMipsSystem : public MipsSystem * PC based event to skip the dprink() call and emulate its * functionality */ - DebugPrintkEvent *debugPrintkEvent; + Linux::DebugPrintkEvent *debugPrintkEvent; /** * Skip calculate_delay_loop() rather than waiting for this to be diff --git a/src/arch/mips/mt.hh b/src/arch/mips/mt.hh index 8828a09a5..d0c333d86 100755 --- a/src/arch/mips/mt.hh +++ b/src/arch/mips/mt.hh @@ -45,7 +45,6 @@ #include "base/misc.hh" #include -using namespace std; namespace MipsISA { @@ -164,7 +163,7 @@ forkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt) success = 1; } } else { - std::cerr << "Bad VPEs" << endl; + std::cerr << "Bad VPEs" << std::endl; } } diff --git a/src/arch/mips/regfile/misc_regfile.cc b/src/arch/mips/regfile/misc_regfile.cc index ea858abf0..a00bf166e 100644 --- a/src/arch/mips/regfile/misc_regfile.cc +++ b/src/arch/mips/regfile/misc_regfile.cc @@ -43,6 +43,7 @@ //#include "params/DerivO3CPU.hh" using namespace std; +using namespace MipsISA; std::string MiscRegFile::miscRegNames[NumMiscRegs] = { -- cgit v1.2.3 From cc95b5739097e31fdaa36a3ff443861969e338b1 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Thu, 5 Mar 2009 19:09:53 -0800 Subject: stats: Fix all stats usages to deal with template fixes --- src/arch/mips/tlb.hh | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh index 1ab9d77e5..dc0babf9a 100644 --- a/src/arch/mips/tlb.hh +++ b/src/arch/mips/tlb.hh @@ -96,14 +96,14 @@ class TLB : public BaseTLB void nextnlu() { if (++nlu >= size) nlu = 0; } MipsISA::PTE *lookup(Addr vpn, uint8_t asn) const; - mutable Stats::Scalar<> read_hits; - mutable Stats::Scalar<> read_misses; - mutable Stats::Scalar<> read_acv; - mutable Stats::Scalar<> read_accesses; - mutable Stats::Scalar<> write_hits; - mutable Stats::Scalar<> write_misses; - mutable Stats::Scalar<> write_acv; - mutable Stats::Scalar<> write_accesses; + mutable Stats::Scalar read_hits; + mutable Stats::Scalar read_misses; + mutable Stats::Scalar read_acv; + mutable Stats::Scalar read_accesses; + mutable Stats::Scalar write_hits; + mutable Stats::Scalar write_misses; + mutable Stats::Scalar write_acv; + mutable Stats::Scalar write_accesses; Stats::Formula hits; Stats::Formula misses; Stats::Formula invalids; -- cgit v1.2.3