From d9856f33a455b9c86b90f5857df866fba3aa5bfb Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Mon, 30 Sep 2013 12:20:43 +0200 Subject: arch: Add support for m5ops using mmapped IPRs In order to support m5ops on virtualized CPUs, we need to either intercept hypercall instructions or provide a memory mapped m5ops interface. Since KVM does not normally pass the results of hypercalls to userspace, which makes that method unfeasible. This changeset introduces support for m5ops using memory mapped mmapped IPRs. This is implemented by adding a class of "generic" IPRs which are handled by architecture-independent code. Such IPRs always have bit 63 set and are handled by handleGenericIprRead() and handleGenericIprWrite(). Platform specific impementations of handleIprRead and handleIprWrite should use GenericISA::isGenericIprAccess to determine if an IPR address should be handled by the generic code instead of the architecture-specific code. Platforms that don't need their own IPR support can reuse GenericISA::handleIprRead() and GenericISA::handleIprWrite(). --- src/arch/mips/mmapped_ipr.hh | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/mmapped_ipr.hh b/src/arch/mips/mmapped_ipr.hh index 4c84d05f2..032fa28b2 100644 --- a/src/arch/mips/mmapped_ipr.hh +++ b/src/arch/mips/mmapped_ipr.hh @@ -37,26 +37,14 @@ * ISA-specific helper functions for memory mapped IPR accesses. */ -#include "base/misc.hh" -#include "mem/packet.hh" +#include "arch/generic/mmapped_ipr.hh" class ThreadContext; namespace MipsISA { - -inline Cycles -handleIprRead(ThreadContext *xc, Packet *pkt) -{ - panic("No implementation for handleIprRead in MIPS\n"); -} - -inline Cycles -handleIprWrite(ThreadContext *xc, Packet *pkt) -{ - panic("No implementation for handleIprWrite in MIPS\n"); -} - + using GenericISA::handleIprRead; + using GenericISA::handleIprWrite; } // namespace MipsISA #endif -- cgit v1.2.3