From dd99ff23c6a71f7173014b5008d0cf12b7ef223a Mon Sep 17 00:00:00 2001
From: Lisa Hsu <hsul@eecs.umich.edu>
Date: Tue, 4 Nov 2008 11:35:42 -0500
Subject: get rid of all instances of readTid() and getThreadNum().  Unify and
 eliminate redundancies with threadId() as their replacement.

---
 src/arch/mips/isa/formats/mt.isa | 4 ++--
 src/arch/mips/locked_mem.hh      | 6 +++---
 src/arch/mips/mt.hh              | 8 ++++----
 src/arch/mips/utility.cc         | 2 +-
 4 files changed, 10 insertions(+), 10 deletions(-)

(limited to 'src/arch/mips')

diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa
index 81fdc2898..1928ee903 100644
--- a/src/arch/mips/isa/formats/mt.isa
+++ b/src/arch/mips/isa/formats/mt.isa
@@ -196,7 +196,7 @@ def format MT_Control(code, *opt_flags) {{
 
 def format MT_MFTR(code, *flags) {{
         flags += ('IsNonSpeculative', )
-#        code = 'std::cerr << curTick << \": T\" << xc->tcBase()->getThreadNum() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
+#        code = 'std::cerr << curTick << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
 
         code += 'if (MT_H == 1) {\n'
         code += 'data = bits(data, top_bit, bottom_bit);\n'
@@ -212,7 +212,7 @@ def format MT_MFTR(code, *flags) {{
 
 def format MT_MTTR(code, *flags) {{
         flags += ('IsNonSpeculative', )
-#        code = 'std::cerr << curTick << \": T\" << xc->tcBase()->getThreadNum() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
+#        code = 'std::cerr << curTick << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
         iop = InstObjParams(name, Name, 'MTOp', code, flags)
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh
index 9f41ba075..021b8cf73 100644
--- a/src/arch/mips/locked_mem.hh
+++ b/src/arch/mips/locked_mem.hh
@@ -52,7 +52,7 @@ handleLockedRead(XC *xc, Request *req)
     xc->setMiscRegNoEffect(LLAddr, req->getPaddr() & ~0xf);
     xc->setMiscRegNoEffect(LLFlag, true);
     DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link Address set to %x.\n",
-            req->getThreadNum(), req->getPaddr() & ~0xf);
+            req->threadId(), req->getPaddr() & ~0xf);
 }
 
 
@@ -94,10 +94,10 @@ handleLockedWrite(XC *xc, Request *req)
 
             if (!lock_flag){
                 DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, Store Conditional Failed.\n",
-                        req->getThreadNum());
+                        req->threadId());
             } else if ((req->getPaddr() & ~0xf) != lock_addr) {
                 DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, Store Conditional Failed.\n",
-                        req->getThreadNum());
+                        req->threadId());
             }
             // store conditional failed already, so don't issue it to mem
             return false;
diff --git a/src/arch/mips/mt.hh b/src/arch/mips/mt.hh
index 20658df28..8828a09a5 100755
--- a/src/arch/mips/mt.hh
+++ b/src/arch/mips/mt.hh
@@ -78,7 +78,7 @@ haltThread(TC *tc)
         // @TODO: Needs to check if this is a branch and if so, take previous instruction
         tc->setMiscReg(TCRestart, tc->readNextPC());
 
-        warn("%i: Halting thread %i in %s @ PC %x, setting restart PC to %x", curTick, tc->getThreadNum(), tc->getCpuPtr()->name(),
+        warn("%i: Halting thread %i in %s @ PC %x, setting restart PC to %x", curTick, tc->threadId(), tc->getCpuPtr()->name(),
              tc->readPC(), tc->readNextPC());
     }
 }
@@ -98,7 +98,7 @@ restoreThread(TC *tc)
         tc->setNextNPC(pc + 8);
         tc->activate(0);
 
-        warn("%i: Restoring thread %i in %s @ PC %x", curTick, tc->getThreadNum(), tc->getCpuPtr()->name(),
+        warn("%i: Restoring thread %i in %s @ PC %x", curTick, tc->threadId(), tc->getCpuPtr()->name(),
              tc->readPC());
     }
 }
@@ -217,7 +217,7 @@ yieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask)
         if (ok == 1) {
             unsigned tcstatus = tc->readMiscRegNoEffect(TCStatus);
             tc->setMiscReg(TCStatus, insertBits(tcstatus, TCS_A, TCS_A, 0));
-            warn("%i: Deactivating Hardware Thread Context #%i", curTick, tc->getThreadNum());
+            warn("%i: Deactivating Hardware Thread Context #%i", curTick, tc->threadId());
         }
     } else if (src_reg > 0) {
         if (src_reg && !yield_mask != 0) {
@@ -238,7 +238,7 @@ yieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask)
             fault = new ThreadFault();
         } else {
             //tc->ScheduleOtherThreads();
-            //std::cerr << "T" << tc->getThreadNum() << "YIELD: Schedule Other Threads.\n" << std::endl;
+            //std::cerr << "T" << tc->threadId() << "YIELD: Schedule Other Threads.\n" << std::endl;
             //tc->suspend();
             // Save last known PC in TCRestart
             // @TODO: Needs to check if this is a branch and if so, take previous instruction
diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc
index 1985c0f43..5908caf68 100644
--- a/src/arch/mips/utility.cc
+++ b/src/arch/mips/utility.cc
@@ -259,7 +259,7 @@ zeroRegisters(CPU *cpu)
 void
 startupCPU(ThreadContext *tc, int cpuId)
 {
-    tc->activate(0/*tc->getThreadNum()*/);
+    tc->activate(0/*tc->threadId()*/);
 }
 
 } // namespace MipsISA
-- 
cgit v1.2.3