From e13d6dc9c0d7a4ae0215f1ee6793eb32570c5169 Mon Sep 17 00:00:00 2001 From: Andrea Mondelli Date: Wed, 6 Mar 2019 10:50:48 -0500 Subject: misc: Removed inconsistency in O3* debug msgs Added consistency in the DEBUG message form, to allow a better parsing. Fixed sn/tid type parameter. Removed some annoying newlines Change-Id: I4761c49fc12b874a7d8b46779475b606865cad4b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17248 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power --- src/arch/mips/isa.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/arch/mips') diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc index 2711712fe..eaee294c8 100644 --- a/src/arch/mips/isa.cc +++ b/src/arch/mips/isa.cc @@ -450,7 +450,7 @@ ISA::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid) unsigned reg_sel = (bankType[misc_reg] == perThreadContext) ? tid : getVPENum(tid); DPRINTF(MipsPRA, - "[tid:%i]: Setting (direct set) CP0 Register:%u " + "[tid:%i] Setting (direct set) CP0 Register:%u " "Select:%u (%s) to %#x.\n", tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val); @@ -463,7 +463,7 @@ ISA::setRegMask(int misc_reg, RegVal val, ThreadID tid) unsigned reg_sel = (bankType[misc_reg] == perThreadContext) ? tid : getVPENum(tid); DPRINTF(MipsPRA, - "[tid:%i]: Setting CP0 Register: %u Select: %u (%s) to %#x\n", + "[tid:%i] Setting CP0 Register: %u Select: %u (%s) to %#x\n", tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val); miscRegFile_WriteMask[misc_reg][reg_sel] = val; } @@ -479,7 +479,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc, ThreadID tid) ? tid : getVPENum(tid); DPRINTF(MipsPRA, - "[tid:%i]: Setting CP0 Register:%u " + "[tid:%i] Setting CP0 Register:%u " "Select:%u (%s) to %#x, with effect.\n", tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val); -- cgit v1.2.3