From 2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2 Mon Sep 17 00:00:00 2001
From: Yasuko Eckert <yasuko.eckert@amd.com>
Date: Tue, 15 Oct 2013 14:22:44 -0400
Subject: cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
---
 src/arch/null/registers.hh | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/arch/null/registers.hh')

diff --git a/src/arch/null/registers.hh b/src/arch/null/registers.hh
index f33b7e5bd..1e52fc5a6 100644
--- a/src/arch/null/registers.hh
+++ b/src/arch/null/registers.hh
@@ -47,6 +47,7 @@ namespace NullISA {
 typedef uint64_t IntReg;
 typedef uint32_t FloatRegBits;
 typedef float FloatReg;
+typedef uint8_t CCReg;
 typedef uint64_t MiscReg;
 
 }
-- 
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