From 835a55e7f347697815fc43851b2dd5a8642d21c4 Mon Sep 17 00:00:00 2001
From: "Timothy M. Jones" <tjones1@inf.ed.ac.uk>
Date: Tue, 27 Oct 2009 09:24:39 -0700
Subject: POWER: Add support for the Power ISA

This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.
---
 src/arch/power/insts/branch.cc | 169 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 169 insertions(+)
 create mode 100644 src/arch/power/insts/branch.cc

(limited to 'src/arch/power/insts/branch.cc')

diff --git a/src/arch/power/insts/branch.cc b/src/arch/power/insts/branch.cc
new file mode 100644
index 000000000..3f4346c97
--- /dev/null
+++ b/src/arch/power/insts/branch.cc
@@ -0,0 +1,169 @@
+/*
+ * Copyright (c) 2009 The University of Edinburgh
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Timothy M. Jones
+ */
+
+#include "arch/power/insts/branch.hh"
+#include "base/loader/symtab.hh"
+
+using namespace PowerISA;
+
+const std::string &
+PCDependentDisassembly::disassemble(Addr pc, const SymbolTable *symtab) const
+{
+    if (!cachedDisassembly ||
+        pc != cachedPC || symtab != cachedSymtab)
+    {
+        if (cachedDisassembly)
+            delete cachedDisassembly;
+
+        cachedDisassembly =
+            new std::string(generateDisassembly(pc, symtab));
+        cachedPC = pc;
+        cachedSymtab = symtab;
+    }
+
+    return *cachedDisassembly;
+}
+
+Addr
+BranchPCRel::branchTarget(Addr pc) const
+{
+    return (uint32_t)(pc + disp);
+}
+
+std::string
+BranchPCRel::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    std::stringstream ss;
+
+    ccprintf(ss, "%-10s ", mnemonic);
+
+    Addr target = pc + disp;
+
+    std::string str;
+    if (symtab && symtab->findSymbol(target, str))
+        ss << str;
+    else
+        ccprintf(ss, "0x%x", target);
+
+    return ss.str();
+}
+
+Addr
+BranchNonPCRel::branchTarget(Addr pc) const
+{
+    return targetAddr;
+}
+
+std::string
+BranchNonPCRel::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    std::stringstream ss;
+
+    ccprintf(ss, "%-10s ", mnemonic);
+
+    std::string str;
+    if (symtab && symtab->findSymbol(targetAddr, str))
+        ss << str;
+    else
+        ccprintf(ss, "0x%x", targetAddr);
+
+    return ss.str();
+}
+
+Addr
+BranchPCRelCond::branchTarget(Addr pc) const
+{
+    return (uint32_t)(pc + disp);
+}
+
+std::string
+BranchPCRelCond::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    std::stringstream ss;
+
+    ccprintf(ss, "%-10s ", mnemonic);
+
+    ss << bo << ", " << bi << ", ";
+
+    Addr target = pc + disp;
+
+    std::string str;
+    if (symtab && symtab->findSymbol(target, str))
+        ss << str;
+    else
+        ccprintf(ss, "0x%x", target);
+
+    return ss.str();
+}
+
+Addr
+BranchNonPCRelCond::branchTarget(Addr pc) const
+{
+    return targetAddr;
+}
+
+std::string
+BranchNonPCRelCond::generateDisassembly(Addr pc,
+                                        const SymbolTable *symtab) const
+{
+    std::stringstream ss;
+
+    ccprintf(ss, "%-10s ", mnemonic);
+
+    ss << bo << ", " << bi << ", ";
+
+    std::string str;
+    if (symtab && symtab->findSymbol(targetAddr, str))
+        ss << str;
+    else
+        ccprintf(ss, "0x%x", targetAddr);
+
+    return ss.str();
+}
+
+Addr
+BranchRegCond::branchTarget(ThreadContext *tc) const
+{
+    uint32_t regVal = tc->readIntReg(_srcRegIdx[_numSrcRegs - 1]);
+    return (regVal & 0xfffffffc);
+}
+
+std::string
+BranchRegCond::generateDisassembly(Addr pc,
+                                   const SymbolTable *symtab) const
+{
+    std::stringstream ss;
+
+    ccprintf(ss, "%-10s ", mnemonic);
+
+    ss << bo << ", " << bi << ", ";
+
+    return ss.str();
+}
-- 
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